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公开(公告)号：US12229000B2
公开(公告)日：2025-02-18
申请号：US18207525
申请日：2023-06-08
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Shane Nowell , Mustafa N. Kaynak , Sampath K. Ratnam , Peter Feeley , Sivagnanam Parthasarathy , Devin M. Batutis , Xiangang Luo
Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including detecting a read error with respect to data residing in a first block of the memory device, wherein the first block is associated with a voltage offset bin; determining a most recently performed error-handling operation performed on a second block associated with the voltage offset bin; and performing the error-handling to recover the data.
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公开(公告)号：US12111724B2
公开(公告)日：2024-10-08
申请号：US17648395
申请日：2022-01-19
Applicant: Micron Technology, Inc.
Inventor： Chun Sum Yeung , Jonathan S. Parry , Deping He , Xiangang Luo , Reshmi Basu
CPC classification number: G06F11/1068 , G06F11/1076
Abstract: Methods, systems, and devices for redundant array management techniques are described. A memory system may include a volatile memory device, a non-volatile memory device, and one or more redundant arrays of independent nodes. The memory system may include a first redundant array controller and a second redundant array controller of a redundant array of independent nodes. The memory system may receive a write command associated with writing data to a type of memory cell. Based on the type of memory cell, the memory system may generate parity data corresponding to the data using one or both of the first redundant array controller and the second redundant array controller. In some examples, the first redundant array controller may be configured to generate parity data associated with a first type of failure and the second redundant array controller may be configured to generate parity data associated with a second type of failure.
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公开(公告)号：US12073107B2
公开(公告)日：2024-08-27
申请号：US17378970
申请日：2021-07-19
Applicant: Micron Technology, Inc.
Inventor： Jianmin Huang , Xiangang Luo , Chun Sum Yeung , Kulachet Tanpairoj
IPC: G06F3/06
CPC classification number: G06F3/0652 , G06F3/0616 , G06F3/0653 , G06F3/0688
Abstract: An apparatus can include a block program erase count (PEC) component. The block PEC component can monitor a quantity of program erase counts (PECs) for each particular type of block of a non-volatile memory array. The block PEC component can further determine which block of the superblock to write host data to next based on the quantity of PECs. The block PEC component can further write host data to the determined block.
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公开(公告)号：US12057185B2
公开(公告)日：2024-08-06
申请号：US18083992
申请日：2022-12-19
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Kishore Kumar Muchherla , Mustafa N. Kaynak , Sivagnanam Parthasarathy , Xiangang Luo , Peter Feeley , Devin M. Batutis , Jiangang Wu , Sampath K. Ratnam , Shane Nowell , Karl D. Schuh
CPC classification number: G11C29/50 , G06F12/0246 , G11C7/1045 , G11C16/26 , G11C29/022
Abstract: A method includes initiating a voltage calibration scan with respect to a block of a memory device, wherein the block is assigned to a first bin associated with a first set of read voltage offsets, and wherein the first bin is designated as a current bin, measuring a value of a data state metric for the block based on a second set of read voltage offsets associated with a second bin having an index value higher than the first bin, determining whether the value is less than a current value of the data state metric measured based on the first set of read voltage offsets, and in response to determining that the value is less than the current value, designating the second bin as the current bin.
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公开(公告)号：US12027213B2
公开(公告)日：2024-07-02
申请号：US17637766
申请日：2021-03-19
Applicant: Micron Technology, Inc.
Inventor： Jie Zhou , Xiangang Luo , Min Rui Ma , Guang Hu
CPC classification number: G11C16/26 , G11C29/028 , G11C29/52
Abstract: Methods, systems, and devices for determining offsets for memory read operations are described. In response to a threshold quantity of pages failing initial reads but being successfully read using a same reference adjustment during re-reads, the offset responsible for the adjustment may be used as a first-applied offset for subsequent re-reads or a baseline offset for subsequent initial reads. After the initial reads begin using the reference adjustment, if a threshold quantity of pages fail initial reads, the offset used for the initial read may be adjusted to be the offset used to perform the successful re-reads. If an updated offset to use a baseline is not identified, the baseline offset may be cleared so the original reference may again be used without adjustment for initial reads.
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Patent Agency Ranking
公开(公告)号：US11995326B2
公开(公告)日：2024-05-28
申请号：US17751026
申请日：2022-05-23
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Karl D. Schuh , Jiangang Wu , Mastafa N. Kaynak , Devin M. Batutis , Xiangang Luo
CPC classification number: G06F3/0631 , G06F3/0604 , G06F3/0679
Abstract: Method includes identifying, while programming sets of pages to dice of memory device, multiple sets of pages experiencing a variation in temporal voltage shift satisfying a threshold criterion; partitioning a set of pages of the multiple sets of pages into a set of fixed-length partitions; storing, in a metadata table, a value to indicate a size of each fixed-length partition; receiving a read operation directed at a page of the set of pages; determining, based on a logical block address of the read operation and on the value that indicates the size of each fixed-length partition, a partition of the set of fixed-length partitions to which the read operation corresponds; and searching within the metadata table to determine a block family to which the partition is assigned, wherein the searching is based on a first value associated with the set of pages and a second value associated with the partition.
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公开(公告)号：US11837307B2
公开(公告)日：2023-12-05
申请号：US17979432
申请日：2022-11-02
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Shane Nowell , Mustafa N. Kaynak , Sampath K. Ratnam , Peter Feeley , Sivagnanam Parthasarathy , Devin M. Batutis , Xiangang Luo
CPC classification number: G11C29/42 , G11C16/102 , G11C16/26 , G11C29/12005 , G11C29/44
Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including performing, on data residing in a block of the memory device, an error-handling operation of a plurality of error-handling operations, wherein an order of the plurality of error-handling operations is based on a voltage offset bin associated with the block, wherein the voltage offset bin defines a set of threshold voltage offsets to be applied to a base voltage read level during read operations; and responsive to determining that the error-handling operation has failed to recover the data, adjusting the order of the plurality of error-handling operations.
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公开(公告)号：US11726867B2
公开(公告)日：2023-08-15
申请号：US17741940
申请日：2022-05-11
Applicant: Micron Technology, Inc.
Inventor： Harish Reddy Singidi , Kishore Kumar Muchherla , Xiangang Luo , Vamsi Pavan Rayaprolu , Ashutosh Malshe
CPC classification number: G06F11/1048 , G06F11/108 , G06F11/1044 , G06F11/1441
Abstract: A variety of applications can include use of parity groups in a memory system with the parity groups arranged for data protection of the memory system. Each parity group can be structured with multiple data pages in which to write data and a parity page in which to write parity data generated from the data written in the multiple data pages. Each data page of a parity group can have storage capacity to include metadata of data written to the data page. Information can be added to the metadata of a data page with the information identifying an asynchronous power loss status of data pages that precede the data page in an order of writing data to the data pages of the parity group. The information can be used in re-construction of data in the parity group following an uncorrectable error correction code error in writing to the parity group.
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公开(公告)号：US11693700B2
公开(公告)日：2023-07-04
申请号：US17234225
申请日：2021-04-19
Applicant: Micron Technology, Inc.
Inventor： Xiangang Luo , Jianmin Huang
CPC classification number: G06F9/5016 , G06F3/0616 , G06F3/0649 , G06F3/0658 , G06F3/0685 , G06F9/30098 , G06F12/0246 , G06F2209/5011
Abstract: Apparatus and methods are disclosed, including using a memory controller to track a maximum logical saturation over the lifespan of the memory device, where logical saturation is the percentage of capacity of the memory device written with data. A portion of a pool of memory cells of the memory device is reallocated from single level cell (SLC) static cache to SLC dynamic cache storage based at least in part on a value of the maximum logical saturation, the reallocating including writing at least one electrical state to a register, in some examples.
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公开(公告)号：US20230176789A1
公开(公告)日：2023-06-08
申请号：US18103857
申请日：2023-01-31
Applicant: Micron Technology, Inc.
Inventor： Ting Luo , Xiangang Luo , Jianmin Huang , Phong S. Nguyen
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0679
Abstract: A method includes receiving a command to write data to a memory device and writing the data to a first memory tier of the memory device. The first memory tier of the memory device is a dynamic memory tier that utilizes single level cells (SLCs), multi-level cells (MLCs), and triple level cells (TLCs). The method further includes migrating the data from the first memory tier of the memory device to a second memory tier of the memory device. The second memory tier of the memory device is a static memory tier that utilizes quad level cells (QLCs).
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