公开(公告)号：US20060133155A1

公开(公告)日：2006-06-22

申请号：US11293376

申请日：2005-12-05

申请人： Norihiro Fujita ,  Hiroshi Nakamura

发明人： Norihiro Fujita ,  Hiroshi Nakamura

IPC分类号： G11C16/04

CPC分类号： G11C16/107 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3445

摘要： A nonvolatile semiconductor memory device comprises memory cell array constituted of a plurality of memory blocks which electrically rewritable memory cells are arranged, before erasing data of all of said memory cells in the selected memory block in a plurality of said memory blocks, preprogram is performed to shift all threshold voltages of all of said memory cells in said selected memory blocks to positive.

摘要翻译： 非易失性半导体存储器件包括由多个存储单元构成的存储单元阵列，所述存储单元阵列在擦除多个所述存储器块中所选择的存储器块中的所有存储单元的数据之前，布置电可重写存储单元， 将所选择的存储器块中的所有存储单元的所有阈值电压移位为正。

公开(公告)号：US20060114729A1

公开(公告)日：2006-06-01

申请号：US11243985

申请日：2005-10-06

申请人： Tomoharu Tanaka ,  Masaki Momodomi ,  Hideo Kato ,  Hiroto Nakai ,  Yoshiyuki Tanaka ,  Riichiro Shirota ,  Seiichi Aritome ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Hiroshi Nakamura ,  Hideko Odaira ,  Yutaka Okamoto ,  Masamichi Asano ,  Kaoru Tokushige

发明人： Tomoharu Tanaka ,  Masaki Momodomi ,  Hideo Kato ,  Hiroto Nakai ,  Yoshiyuki Tanaka ,  Riichiro Shirota ,  Seiichi Aritome ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Hiroshi Nakamura ,  Hideko Odaira ,  Yutaka Okamoto ,  Masamichi Asano ,  Kaoru Tokushige

IPC分类号： G11C7/10 ,  G11C11/34

CPC分类号： G11C29/785 ,  G06F11/1008 ,  G06F11/1068 ,  G06F2201/81 ,  G06F2212/2022 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  G11C29/34 ,  G11C29/52

摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

公开(公告)号：US20060067044A1

公开(公告)日：2006-03-30

申请号：US11236009

申请日：2005-09-27

申请人： Mitsuhiro Yoshida ,  Hiroshi Nakamura ,  Shinichi Kido

发明人： Mitsuhiro Yoshida ,  Hiroshi Nakamura ,  Shinichi Kido

IPC分类号： G06F1/16

CPC分类号： G06F1/1632

摘要： A supporting apparatus includes a connector, a first hook portion and a second hook portion. The connector is connected to a signal terminal provided at a bottom portion of a portable computer that is chosen from a plurality of electronic devices having different sizes which are dimensions measured from the bottom portions to outer peripheral edges of the portable computes. The first hook portion is provided with respect to the connector in a position corresponding to that of the outer peripheral edge of one of the portable computers. The second hook portion is provided with respect to the connector in a position corresponding to the outer peripheral edge of another of the portable computers.

摘要翻译： 支撑装置包括连接器，第一钩部和第二钩部。 连接器连接到设置在便携式计算机的底部的信号端子，该信号端子是从具有不同尺寸的多个电子设备中选择的，这些电子设备是从便携式计算机的底部到外围边缘测量的尺寸。 第一钩部相对于连接器设置在与便携式计算机之一的外围边缘相对应的位置。 第二钩部相对于连接器设置在与另一个便携式计算机的外围边缘对应的位置。

公开(公告)号：US07016228B2

公开(公告)日：2006-03-21

申请号：US10699398

申请日：2003-10-31

申请人： Koichi Kawai ,  Kenichi Imamiya ,  Hiroshi Nakamura

发明人： Koichi Kawai ,  Kenichi Imamiya ,  Hiroshi Nakamura

IPC分类号： G11C16/04

CPC分类号： G11C16/105 ,  G11C7/1006 ,  G11C7/1021 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C16/102 ,  G11C16/3431 ,  H01L27/115

摘要： Data read from memory cells of one page in a memory cell array that corresponds to a page address of a copy source is sensed and latched by a sense/latch circuit. The sense/latch circuit has a plurality of latch circuits, and the plurality of latch circuits is specified according to the column address. The latch circuit specified in accordance with the column address is supplied with the data to be rewritten. The latch circuit specified in accordance with its address latches the data to be rewritten, whereby rewriting of the data is performed. The data of one page after rewritten is written into the page in the memory cell array that corresponds to the page address of a copy destination.

公开(公告)号：US07009878B2

公开(公告)日：2006-03-07

申请号：US10664977

申请日：2003-09-22

申请人： Koji Hosono ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Kenichi Imamiya

发明人： Koji Hosono ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Kenichi Imamiya

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C5/145 ,  G11C7/1006 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5641 ,  G11C2211/5642 ,  G11C2211/5643

摘要： A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has a first latch and a second latch that are selectively connected to the memory cell array and transfer data each other. A controller controls the reprogramming and retrieval circuits on data-reprogramming operation to and data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches in storing the two-bit four-level data in one of the memory cells in a predetermined threshold level range. In the caching operation mode, data transfer between one of the memory cells selected in accordance with a first address and the first latch is performed while data transfer is performed between the second latch and input/output terminals in accordance with a second address with respect to one-bit two-level data to be stored in one of the memory cells.

摘要翻译： 非易失性半导体器件具有存储单元阵列，其具有电可擦除可编程非易失性存储器单元，重新编程和检索电路，其临时存储要存储在存储单元阵列中的要编程的数据并感测从存储器单元阵列检索的数据。 每个重新编程和检索电路具有选择性地连接到存储单元阵列并且彼此传送数据的第一锁存器和第二锁存器。 一个控制器控制重新编程和检索电路的数据重新编程操作和数据检索操作从存储单元阵列。 每个重新编程和检索电路都具有多级逻辑操作模式和缓存操作模式。 在多级逻辑操作模式中，使用第一和第二锁存器在存储单元之一中存储两位四电平数据来执行二位四电平数据的高位和低位的重新编程和检索 在预定的阈值电平范围内。 在高速缓存操作模式中，根据第一地址选择的存储器单元之一和第一锁存器之间的数据传输是在第二锁存器和输入/输出端子之间根据第二地址相对于 要存储在其中一个存储单元中的一位二电平数据。

公开(公告)号：US20060044288A1

公开(公告)日：2006-03-02

申请号：US10871080

申请日：2004-06-18

申请人： Hiroshi Nakamura ,  Toshiyuki Tanaka

发明人： Hiroshi Nakamura ,  Toshiyuki Tanaka

IPC分类号： G09G5/00

CPC分类号： G06F3/03545 ,  G06F1/1626 ,  G06F1/1628 ,  G06F1/166 ,  G06F1/169 ,  G06F3/0338 ,  G06F2200/1614 ,  G06F2200/1632

摘要： According to one embodiment of the invention, an electronic device, such as a tablet PC for example, is designed with a housing and a cover configured for attachment to the housing. The housing includes a front panel and a back panel having a base unit with a recess to receive a stylus pen to operate as a leg to maintain the housing in an upright position. Alternatively, the housing may include a control button to receive a stylus pen so that the combination operates as an input device similar to a joystick.

摘要翻译： 根据本发明的一个实施例，例如诸如平板电脑的电子设备被设计成具有被配置为附接到壳体的壳体和盖子。 壳体包括前面板和后面板，后面板具有带有凹部的基座单元，用于接收触控笔以作为腿部维持壳体处于直立位置。 或者，壳体可以包括用于接收触针笔的控制按钮，使得该组合作为类似于操纵杆的输入装置操作。

公开(公告)号：US20060022745A1

公开(公告)日：2006-02-02

申请号：US11184918

申请日：2005-07-20

申请人： Hiroshi Nakamura

发明人： Hiroshi Nakamura

IPC分类号： G05F1/10

CPC分类号： G05F3/247

摘要： A semiconductor integrated circuit device includes: a circuit node to be set at a certain operating voltage; and a voltage stabilizing capacitor connected to the circuit node, wherein the voltage stabilizing capacitor is formed of at least two MOS capacitors coupled in parallel with each other, which show different capacitance changes from each other in accordance with an applied voltage change.

摘要翻译： 一种半导体集成电路器件，包括：要设置在一定工作电压的电路节点; 以及连接到所述电路节点的稳压电容器，其中所述稳压电容器由至少两个彼此并联耦合的MOS电容器形成，所述至少两个MOS电容器根据施加的电压变化显示彼此不同的电容变化。

公开(公告)号：US06984975B2

公开(公告)日：2006-01-10

申请号：US10683734

申请日：2003-10-10

申请人： Fusayoshi Aruga ,  Junichi Nakajyo ,  Shogo Momose ,  Hiroshi Nakamura

发明人： Fusayoshi Aruga ,  Junichi Nakajyo ,  Shogo Momose ,  Hiroshi Nakamura

IPC分类号： G01B7/14

CPC分类号： G01D5/204

摘要： A displacement sensor for sensing the relative position of an object to be detcted is provided. The displacement sensor includes a core body having a core center portion and core end portions that are continuously formed on both sides of the core center portion. Magnetizing coils and detecting coils are wound around the core body such that they are lined on an axis of the core body. One of the magnetizing coils and detecting coils is placed at the core center portion while the other ones of the magnetizing coils and detctin coils are placed at the core end portions in the axial direction. The width of the core end portions in the direction perpendicular to the axial direction of the core body is substantially the same and is smaller than the width of the core center portion.

摘要翻译： 提供了用于感测被检测物体的相对位置的位移传感器。 位移传感器包括具有芯部中心部分的芯体和连续地形成在芯部中心部分两侧的芯部端部。 磁化线圈和检测线圈缠绕在芯体上，使得它们被排列在芯体的轴线上。 磁化线圈和检测线圈中的一个放置在芯中心部分，而另一个磁化线圈和定子线圈被放置在轴向的芯部端部。 芯端部在与芯体的轴向垂直的方向上的宽度大致相同且小于芯心部的宽度。

公开(公告)号：US06980423B2

公开(公告)日：2005-12-27

申请号：US10717329

申请日：2003-11-18

申请人： Toshiyuki Tanaka ,  Hiroshi Nakamura ,  Martin P. Riddiford

发明人： Toshiyuki Tanaka ,  Hiroshi Nakamura ,  Martin P. Riddiford

IPC分类号： G06F1/16

CPC分类号： G06F1/162 ,  G06F1/1679 ,  G06F1/1688 ,  G06F2200/1614 ,  Y10S248/917 ,  Y10T292/0849 ,  Y10T292/11

摘要： An apparatus has a body having a channel. A display support member has a first end pivotally coupled to the body and a second end. A display housing has a bottom portion. The display housing is pivotally coupled to the second end of the display support member. A first latch member is coupled to the bottom portion of the display housing. The first latch member is adapted to be received by the channel and hold the display housing.

摘要翻译： 装置具有具有通道的主体。 显示器支撑构件具有枢转地联接到主体的第一端和第二端。 显示器壳体具有底部。 显示器壳体枢转地联接到显示器支撑构件的第二端。 第一闩锁构件联接到显示器壳体的底部。 第一闩锁构件适于被通道接收并且保持显示器壳体。

公开(公告)号：US06967892B2

公开(公告)日：2005-11-22

申请号：US10804094

申请日：2004-03-19

申请人： Tomoharu Tanaka ,  Masaki Momodomi ,  Hideo Kato ,  Hiroto Nakai ,  Yoshiyuki Tanaka ,  Riichiro Shirota ,  Seiichi Aritome ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Hiroshi Nakamura ,  Hideko Odaira ,  Yutaka Okamoto ,  Masamichi Asano ,  Kaoru Tokushige

发明人： Tomoharu Tanaka ,  Masaki Momodomi ,  Hideo Kato ,  Hiroto Nakai ,  Yoshiyuki Tanaka ,  Riichiro Shirota ,  Seiichi Aritome ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Hiroshi Nakamura ,  Hideko Odaira ,  Yutaka Okamoto ,  Masamichi Asano ,  Kaoru Tokushige

IPC分类号： G06F11/10 ,  G11C16/10 ,  G11C16/12 ,  G11C16/34 ,  G11C29/00 ,  G11C29/34 ,  G11C29/52 ,  G11C16/04

CPC分类号： G11C29/785 ,  G06F11/1008 ,  G06F11/1068 ,  G06F2201/81 ,  G06F2212/2022 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  G11C29/34 ,  G11C29/52

摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite oepration, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

摘要翻译： 可以缩短程序验证和擦除验证操作所需的时间。 即使重复执行写入和擦除操作，也可以抑制存储单元的阈值变化。 在编程和擦除操作之后，可以根据每个位线上的电位的预充电之后的所有位线同时判断操作，而不改变列地址。 在数据重写过程中，通过改变数据寄存器中的数据，对数据一次正确写入的存储单元不会影响重写操作。