-
公开(公告)号：US11107817B2
公开(公告)日：2021-08-31
申请号：US16298947
申请日：2019-03-11
发明人： Kamal M. Karda , Yi Fang Lee , Haitao Liu , Durai Vishak Nirmal Ramaswamy , Ramanathan Gandhi , Karthik Sarpatwari , Scott E. Sills , Sameer Chhajed
IPC分类号： H01L27/105 , H01L27/092 , H01L27/12 , H01L29/66 , H01L29/267 , H01L29/423 , H01L29/786 , H01L29/24
摘要： Some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. The second semiconductor material is a different composition than the first semiconductor material. Hydrogen is diffused within the first and second semiconductor materials. The conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source/drain regions, and having the first semiconductor material as a channel region between the source/drain regions. A transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. Some embodiments include methods of forming integrated assemblies.
-
公开(公告)号：US20210233584A1
公开(公告)日：2021-07-29
申请号：US17165555
申请日：2021-02-02
IPC分类号： G11C13/00
摘要： Methods, systems, and devices for dirty write on power off are described. In an example, the described techniques may include writing memory cells of a device according to one or more parameters (e.g., reset current amplitude), where each memory cell is associated with a storage element storing a value based on a material property associated with the storage element. Additionally, the described techniques may include identifying, after writing the memory cells, an indication of power down for the device and refreshing, before the power down of the device, a portion of the memory cells based on identifying the indication of the power down for the device. In some cases, refreshing includes modifying at least one of the one or more parameters for a write operation for the portion of the memory cells.
-
公开(公告)号：US20210151107A1
公开(公告)日：2021-05-20
申请号：US17089146
申请日：2020-11-04
摘要： Methods, systems, and devices for memory cell selection to enable a memory device to select a targeted memory cell during a write operation are described. The memory device may apply a first pulse to a selected bit line of the targeted memory cell while applying a voltage to deselected word lines to prevent current leakage. If the targeted memory is not selected after the first pulse, the memory device may apply a second pulse to the selected bit line while applying a voltage to the deselected word lines. If the targeted memory cell is not selected following the second pulse, the memory device may apply a third pulse to the selected bit line while applying the voltage to the deselected word lines. The memory device may detect a snapback event after any of the pulses if the targeted memory cell is selected.
-
74.发明公开公开(公告)号：US20240233797A1
公开(公告)日：2024-07-11
申请号：US18615490
申请日：2024-03-25
IPC分类号： G11C11/402 , G11C11/409 , H01L29/22 , H01L29/78 , H10B99/00
CPC分类号： G11C11/4023 , G11C11/409 , H01L29/22 , H01L29/7827 , H10B99/00
摘要： Some embodiments include apparatuses and methods operating the apparatuses. One of the apparatuses includes a first data line located over a substrate, a second data line located over the first data line, a third data line located over the second data line and electrically separated from the first and second data lines, and a memory cell coupled to the first, second, and third data lines. The memory cell includes a first material between the first and second data lines and electrically coupled to the first and second data lines; a second material located over the first data line and the first material, the second material electrically separated from the first material and electrically coupled to the third data line; and a memory element electrically coupled to the second material and electrically separated from the first material and first and second data lines.
-
公开(公告)号：US11985806B2
公开(公告)日：2024-05-14
申请号：US16721380
申请日：2019-12-19
发明人： Kamal M. Karda , Srinivas Pulugurtha , Haitao Liu , Karthik Sarpatwari , Durai Vishak Nirmal Ramaswamy
IPC分类号： H01L27/108 , H10B12/00 , G11C11/402
CPC分类号： H10B12/01 , G11C11/4023
摘要： Some embodiments include apparatuses and methods of forming the apparatus. One of the apparatuses and methods includes a memory cell having a first transistor and a second transistor located over a substrate. The first transistor includes a channel region. The second transistor includes a channel region located over the channel region of the first transistor and electrically separated from the first channel region. The memory cell includes a memory element located on at least one side of the channel region of the first transistor. The memory element is electrically separated from the channel region of the first transistor, and electrically coupled to the channel of the second transistor.
-
公开(公告)号：US11942139B2
公开(公告)日：2024-03-26
申请号：US18075570
申请日：2022-12-06
IPC分类号： G11C11/406 , G11C11/4074 , G11C11/4091
CPC分类号： G11C11/40622 , G11C11/40615 , G11C11/4074 , G11C11/4091
摘要： The present disclosure includes apparatuses, methods, and systems for performing refresh operations on memory cells. An embodiment includes a memory having a group of memory cells and one or more additional memory cells whose data state is indicative of whether to refresh the group of memory cells, and circuitry configured to apply a first voltage pulse to the group of memory cells to sense a data state of the memory cells of the group, apply, while the first voltage pulse is applied to the group of memory cells, a second voltage pulse having a greater magnitude than the first voltage pulse to the one or more additional memory cells to sense a data state of the one or more additional memory cells, and determine whether to perform a refresh operation on the group of memory cells based on the sensed data state of the one or more additional memory cells.
-
公开(公告)号：US20240074216A1
公开(公告)日：2024-02-29
申请号：US18387921
申请日：2023-11-08
发明人： Kamal M. Karda , Yi Fang Lee , Haitao Liu , Durai Vishak Nirmal Ramaswamy , Ramanathan Gandhi , Karthik Sarpatwari , Scott E. Sills , Sameer Chhajed
IPC分类号： H10B99/00 , H01L27/092 , H01L27/12 , H01L29/24 , H01L29/267 , H01L29/423 , H01L29/66 , H01L29/786
CPC分类号： H10B99/00 , H01L27/092 , H01L27/1207 , H01L27/1225 , H01L27/124 , H01L27/1255 , H01L27/1259 , H01L29/24 , H01L29/267 , H01L29/42392 , H01L29/66969 , H01L29/78642 , H01L29/7869
摘要： Some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. The second semiconductor material is a different composition than the first semiconductor material. Hydrogen is diffused within the first and second semiconductor materials. The conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source/drain regions, and having the first semiconductor material as a channel region between the source/drain regions. A transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. Some embodiments include methods of forming integrated assemblies.
-
公开(公告)号：US11871589B2
公开(公告)日：2024-01-09
申请号：US17745298
申请日：2022-05-16
IPC分类号： H01L27/00 , H01L29/00 , H10B99/00 , H01L27/12 , H01L29/788 , H01L29/24 , H01L29/786
CPC分类号： H10B99/00 , H01L27/124 , H01L27/1225 , H01L27/1251 , H01L29/24 , H01L29/7869 , H01L29/7881 , H01L29/78672
摘要： Some embodiments include apparatuses and methods using a substrate, a pillar having a length perpendicular to the substrate, a first conductive plate, a second conductive plate, a memory cell located between the first and second conductive plates and electrically separated from the first and second conductive plates, and a conductive connection. The first conductive plate is located in a first level of the apparatus and being separated from the pillar by a first dielectric located in the first level. The second conductive plate is located in a second level of the apparatus and being separated from the pillar by a second dielectric located in the second level. The memory cell includes a first semiconductor material located in a third level of the apparatus between the first and second levels and contacting the pillar and the conductive connection, and a second semiconductor material located in a fourth level of the apparatus between the first and second levels and contacting the pillar.
-
公开(公告)号：US20230361118A1
公开(公告)日：2023-11-09
申请号：US17661979
申请日：2022-05-04
IPC分类号： H01L27/092 , H01L29/78
CPC分类号： H01L27/092 , H01L29/7827
摘要： A microelectronic device comprises vertical inverter comprising a pillar structure vertically extending above a first conductive line. The pillar structure comprises a first vertical transistor vertically overlying and in electrical communication with the first conductive line, a second conductive line vertically overlying the first conductive line and electrically isolated from the first conductive line by a dielectric material, the second conductive line configured to be coupled to a ground structure, a second vertical transistor horizontally neighboring the first vertical transistor and in electrical communication with the second conductive line, the second vertical transistor horizontally spaced from the first vertical transistor by the dielectric material, and at least one electrode horizontally extending along a channel region of the first vertical transistor and an additional channel region of the second vertical transistor. Related microelectronic devices and electronic systems are also described.
-
公开(公告)号：US20230299163A1
公开(公告)日：2023-09-21
申请号：US17655479
申请日：2022-03-18
发明人： Kamal M. Karda , Haitao Liu , Durai Vishak Nirmal Ramaswamy , Karthik Sarpatwari , Richard E. Fackenthal
IPC分类号： H01L29/423 , H01L27/02 , H01L27/11 , G11C5/02 , H01L27/092
CPC分类号： H01L29/42372 , G11C5/025 , H01L27/0207 , H01L27/092 , H01L27/1104
摘要： An inverter includes a transistor, an additional transistor overlying the transistor, and a hybrid gate electrode interposed between and shared by the transistor and the additional transistor. The hybrid gate electrode includes a region overlying a channel structure of the transistor, an additional region overlying the region and underlying an additional channel structure of the additional transistor, and further region interposed between the region and the additional region. The region has a first material composition. The additional region has a second material composition different than the first material composition of the region. Memory devices and electronic systems are also described.
-
-
-
-
-
-
-
-
-
搜索结果
136 条记录 (耗时 0.02 秒)
