公开(公告)号：US10430262B2

公开(公告)日：2019-10-01

申请号：US16178963

申请日：2018-11-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael G. Miller ,  Ashutosh Malshe ,  Violante Moschiano ,  Peter Feeley ,  Gary F. Besinga ,  Sampath K. Ratnam ,  Walter Di-Francesco ,  Renato C. Padilla, Jr. ,  Yun Li ,  Kishore Kumar Muchherla

IPC: G11C16/10 ,  G06F11/07 ,  G06F3/06 ,  G06F11/10 ,  G11C11/56 ,  G11C16/22 ,  G11C16/30 ,  G11C16/34 ,  G11C5/14

Abstract: Apparatus having an array of memory cells include a controller configured to read a particular memory cell of a last written page of memory cells of a block of memory cells of the array of memory cells, determine whether a threshold voltage of the particular memory cell is less than a particular voltage level, and mark the last written page of memory cells as affected by power loss during a programming operation of the last written page of memory cells when the threshold voltage of the particular memory cell is determined to be higher than the particular voltage level.

公开(公告)号：US10430116B2

公开(公告)日：2019-10-01

申请号：US15693121

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Michael G. Miller ,  Kishore Kumar Muchherla ,  Harish Singidi ,  Sampath Ratnam ,  Renato C. Padilla, Jr. ,  Gary F. Besinga ,  Peter Sean Feeley

IPC: G06F3/06 ,  G11C16/10 ,  G11C5/14 ,  G11C16/04 ,  G11C16/30 ,  G11C16/34 ,  G11C16/08

Abstract: Devices and techniques for correcting for power loss in NAND memory devices are disclosed herein. The NAND memory devices may comprise a number of physical pages. For example, a memory controller may detect a power loss indicator at the NAND flash memory. The memory controller may identify a last-written physical page and determine whether the last-written physical page comprises more than a threshold number of low-read-margin cells. If the last-written physical page comprises more than the threshold number of low-read-margin cells, the memory controller may provide a programming voltage to at least the low-read-margin cells.

公开(公告)号：US20190278490A1

公开(公告)日：2019-09-12

申请号：US16420505

申请日：2019-05-23

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Ashutosh Malshe ,  Preston A. Thomson ,  Michael G. Miller ,  Sampath K. Ratnam ,  Renato C. Padilla ,  Peter Feeley

IPC: G06F3/06 ,  G11C11/56 ,  G11C16/34 ,  G11C16/16 ,  G11C16/10

Abstract: The present disclosure includes memory blocks erasable in a single level cell mode. A number of embodiments include a memory comprising a plurality of mixed mode blocks and a controller. The controller may be configured to identify a particular mixed mode block for an erase operation and, responsive to a determined intent to subsequently write the particular mixed mode block in a single level cell (SLC) mode, perform the erase operation in the SLC mode.

公开(公告)号：US20190250824A1

公开(公告)日：2019-08-15

申请号：US16396432

申请日：2019-04-26

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Ashutosh Malshe ,  Sampath K. Ratnam ,  Peter Feeley ,  Michael G. Miller ,  Christopher S. Hale ,  Renato C. Padilla

IPC: G06F3/06 ,  G06F12/0888 ,  G06F12/0893 ,  G06F12/02 ,  G06F11/34

CPC classification number: G06F3/0604 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/34 ,  G06F12/0246 ,  G06F12/0888 ,  G06F12/0893 ,  G06F2201/885 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/222 ,  G06F2212/502 ,  G06F2212/601 ,  G06F2212/7205 ,  G06F2212/7206

Abstract: Memory devices are disclosed. A memory device may include main memory and a hybrid cache. The hybrid cache includes a dynamic cache including x-level cell (XLC) blocks of non-volatile memory cells shared between the dynamic cache and the main memory. The hybrid cache further includes a static cache including single-level cell (SLC) blocks of non-volatile memory cells. The memory device further includes a memory controller configured to disable at least one of the static cache and the dynamic cache responsive to a workload of the hybrid cache relative to a Total Bytes Written (TBW) Spec for the memory device. Methods of operating a memory device and an electronic system are also described.

公开(公告)号：US10380018B2

公开(公告)日：2019-08-13

申请号：US15478631

申请日：2017-04-04

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Sampath K. Ratnam ,  Peter Feeley ,  Michael G. Miller ,  Daniel J. Hubbard ,  Renato C. Padilla ,  Ashutosh Malshe ,  Harish R. Singidi

IPC: G06F3/06 ,  G06F12/02

Abstract: An example apparatus for garbage collection can include a memory including a plurality of mixed mode blocks. The example apparatus can include a controller. The controller can be configured to write a first portion of sequential host data to the plurality of mixed mode blocks of the memory in a single level cell (SLC) mode. The controller can be configured to write a second portion of sequential host data to the plurality of mixed mode blocks in an XLC mode. The controller can be configured to write the second portion of sequential host data by performing a garbage collection operation. The garbage collection operation can include adding more blocks to a free block pool than a quantity of blocks that are written to in association with writing the second portion of sequential host data to the plurality of mixed mode blocks.

公开(公告)号：US20190237146A1

公开(公告)日：2019-08-01

申请号：US16381682

申请日：2019-04-11

Applicant: Micron Technology, Inc.

Inventor： Ashutosh Malshe ,  Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Michael G. Miller ,  Sampath Ratman ,  Xu Zhang ,  Jie Zhou

IPC: G11C16/26 ,  G06F11/22 ,  G06F12/02 ,  G11C7/06 ,  G06F11/07 ,  G11C16/34

Abstract: Devices and techniques for initiating and controlling preemptive idle time read scans in a flash based storage system are disclosed. In an example, a memory device includes a NAND memory array and a memory controller to schedule and initiate read scans among multiple locations of the memory array, with such read scans being preemptively triggered during an idle (background) state of the memory device, thus reducing host latency during read and write operations in an active (foreground) state of the memory device. In an example, the optimization technique includes scheduling a read scan operation, monitoring an active or idle state of host IO operations, and preemptively initiating the read scan operation when entering an idle state, before the read scan operation is scheduled to occur. In further examples, the read scan may preemptively occur based on time-based scheduling, frequency-based conditions, or event-driven conditions triggering the read scan.

公开(公告)号：US10325668B2

公开(公告)日：2019-06-18

申请号：US15479356

申请日：2017-04-05

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Ashutosh Malshe ,  Preston A. Thomson ,  Michael G. Miller ,  Gary F. Besinga ,  Scott A. Stoller ,  Sampath K. Ratnam ,  Renato C. Padilla ,  Peter Feeley

IPC: G11C16/34

Abstract: Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.

公开(公告)号：US10303535B2

公开(公告)日：2019-05-28

申请号：US15911490

申请日：2018-03-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael G. Miller ,  Ashutosh Malshe ,  Violante Moschiano ,  Peter Feeley ,  Gary F. Besinga ,  Sampath K. Ratnam ,  Walter Di-Francesco ,  Renato C. Padilla, Jr. ,  Yun Li ,  Kishore Kumar Muchherla

IPC: G11C29/50 ,  G06F11/07 ,  G06F3/06

Abstract: Apparatus include controllers configured to iteratively program a group of memory cells to respective desired data states; determine whether a power loss to the apparatus is indicated while iteratively programming the group of memory cells; and if a power loss to the apparatus is indicated, to change the desired data state of the particular memory cell before continuing with the programming. Apparatus further include controllers configured to read a particular memory cell of a last written page of memory cells, determine whether a threshold voltage of the particular memory cell is less than a particular voltage level, and to mark the last written page of memory cells as affected by power loss during a programming operation of the last written page of memory cells when the threshold voltage of the particular memory cell is determined to be higher than the particular voltage level.

公开(公告)号：US20190103164A1

公开(公告)日：2019-04-04

申请号：US15571232

申请日：2017-09-30

Applicant: Micron Technology, Inc.

Inventor： Ashutosh Malshe ,  Harish Singidi ,  Kishore Kumar Muchherla ,  Michael G. Miller ,  Sampath Ratnam ,  John Zhang ,  Jie Zhou

IPC: G11C16/26 ,  G06F12/02 ,  G11C7/06 ,  G06F11/07

Abstract: Devices and techniques for initiating and controlling preemptive idle time read scans in a flash based storage system are disclosed. In an example, a memory device includes a NAND memory array and a memory controller to schedule and initiate read scans among multiple locations of the memory array, with such read scans being preemptively triggered during an idle (background) state of the memory device, thus reducing host latency during read and write operations in an active (foreground) state of the memory device. In an example, the optimization technique includes scheduling a read scan operation, monitoring an active or idle state of host IO operations, and preemptively initiating the read scan operation when entering an idle state, before the read scan operation is scheduled to occur. In further examples, the read scan may preemptively occur based on time-based scheduling, frequency-based conditions, or event-driven conditions triggering the read scan.

公开(公告)号：US12131020B2

公开(公告)日：2024-10-29

申请号：US17457615

申请日：2021-12-03

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Ashutosh Malshe ,  Sampath K. Ratnam ,  Peter Feeley ,  Michael G. Miller ,  Christopher S. Hale ,  Renato C. Padilla

IPC: G06F3/06 ,  G06F11/34 ,  G06F12/02 ,  G06F12/0888 ,  G06F12/0893

CPC classification number: G06F3/0604 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/34 ,  G06F11/348 ,  G06F12/0246 ,  G06F12/0888 ,  G06F12/0893 ,  G06F2201/885 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/222 ,  G06F2212/502 ,  G06F2212/601 ,  G06F2212/7205 ,  G06F2212/7206

Abstract: Memory devices are disclosed. A memory device may include dynamic cache, static cache, and a memory controller. The memory controller may be configured to disable the static cache responsive to a number of program/erase (PE) cycles consumed by the static cache being greater than an endurance of the static cache. The memory controller may also be configured to disable the dynamic cache responsive to a number of PE cycles consumed by the dynamic cache being greater than an endurance of the dynamic cache. Associated methods and systems are also disclosed.