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    SPLIT PILLAR ARCHITECTURES FOR MEMORY DEVICES
    72.
    发明申请
    SPLIT PILLAR ARCHITECTURES FOR MEMORY DEVICES 有权

    公开(公告)号：US20250107105A1

    公开(公告)日：2025-03-27

    申请号：US18954089

    申请日：2024-12-13

    Applicant: Micron Technology, Inc.

    Inventor： Paolo Fantini ,  Fabio Pellizzer ,  Lorenzo Fratin

    IPC: H10B63/00 ,  G11C13/00 ,  H10B20/00 ,  H10N70/00

    Abstract: Methods, systems, and devices for split pillar architectures for memory devices are described. A memory device may include a substrate arranged with conductive contacts in a pattern and openings through alternative layers of conductive and insulative material that may decrease the spacing between the openings while maintaining a dielectric thickness to sustain the voltage to be applied to the array. After etching material, an insulative material may be deposited in a trench. Portions of the insulative material may be removed to form openings, into which cell material is deposited. Conductive pillars may extend perpendicular to the planes of the conductive material and the substrate, and couple to conductive contacts. The conductive pillars may be divided to form first and second pillars.

    SELF-SELECTING MEMORY ARRAY WITH HORIZONTAL ACCESS LINES
    73.
    发明申请
    SELF-SELECTING MEMORY ARRAY WITH HORIZONTAL ACCESS LINES 有权

    公开(公告)号：US20250061943A1

    公开(公告)日：2025-02-20

    申请号：US18814164

    申请日：2024-08-23

    Applicant: Micron Technology, Inc.

    Inventor： Lorenzo Fratin ,  Fabio Pellizzer ,  Agostino Pirovano ,  Russell L. Meyer

    IPC: G11C13/00 ,  H01L23/528

    Abstract: Methods, systems, and devices for self-selecting memory with horizontal access lines are described. A memory array may include first and second access lines extending in different directions. For example, a first access line may extend in a first direction, and a second access line may extend in a second direction. At each intersection, a plurality of memory cells may exist, and each plurality of memory cells may be in contact with a self-selecting material. Further, a dielectric material may be positioned between a first plurality of memory cells and a second plurality of memory cells in at least one direction. each cell group (e.g., a first and second plurality of memory cells) may be in contact with one of the first access lines and second access lines, respectively.

    Folded access line for memory cell access in a memory device
    74.
    发明授权
    Folded access line for memory cell access in a memory device 有权

    公开(公告)号：US12219782B2

    公开(公告)日：2025-02-04

    申请号：US17536927

    申请日：2021-11-29

    Applicant: Micron Technology, Inc.

    Inventor： Srivatsan Venkatesan ,  Fabio Pellizzer

    IPC: H10B63/00 ,  H10N70/00

    Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Spike current suppression is implemented using a folded access line structure. Each access line includes integrated top and bottom insulating layers that restrict current flow to the memory cells through a narrower middle portion of the access line. For near memory cells located overlying or underlying the insulating layers, the resistance to each memory cell is increased because the cell is accessed using only the higher resistance path of the meandering, folded circuit path that flows through the middle portion. Spike discharge that occurs when the memory cell is selected is reduced by this higher resistance path.

    Memory device and method for manufacturing the same
    75.
    发明授权
    Memory device and method for manufacturing the same 有权

    公开(公告)号：US12150317B2

    公开(公告)日：2024-11-19

    申请号：US17431661

    申请日：2020-07-22

    Applicant: Micron Technology, Inc.

    Inventor： Lorenzo Fratin ,  Paolo Fantini ,  Fabio Pellizzer

    IPC: H01L27/24 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

    Abstract: Methods for, apparatuses with, and vertical 3D memory devices are described. A vertical 3D memory device may comprise: a plurality of contacts associated with a plurality of digit lines and extending through a substrate; a plurality of word line plates separated from one another by respective dielectric layers and including a first plurality of word line plates and a second plurality of word line plates; a dielectric material positioned between the first plurality and the second plurality of word line plates, the dielectric material extending in a serpentine shape over the substrate; a plurality of pillars formed over and coupled with the plurality of contacts; and a plurality of storage elements each comprising chalcogenide material positioned in a recess between a respective word line plate and a respective pillar, wherein the recess is of an arch-shape, and the chalcogenide material in the recess contacts the respective word line plate.

    Decoding for a memory device
    76.
    发明授权
    Decoding for a memory device 有权

    公开(公告)号：US12148467B2

    公开(公告)日：2024-11-19

    申请号：US17885136

    申请日：2022-08-10

    Applicant: Micron Technology, Inc.

    Inventor： Paolo Fantini ,  Lorenzo Fratin ,  Fabio Pellizzer

    IPC: G11C13/00 ,  H10B63/00 ,  H10N70/00

    Abstract: Methods, systems, and devices for decoding for a memory device are described. A decoder may include a first vertical n-type transistor and a second vertical n-type transistor that extends in a third direction relative to a die of a memory array. The first vertical n-type transistor may be configured to selectively couple an access line with a source node and the second n-type transistor may be configured to selectively couple the access line with a ground node. To activate the access line coupled with the first and second vertical n-type transistors, the first vertical n-type transistor may be activated, the second vertical n-type transistor may be deactivated, and the source node coupled with the first vertical n-type transistor may have a voltage applied that differs from a ground voltage.

    READING A MULTI-LEVEL MEMORY CELL
    77.
    发明公开
    READING A MULTI-LEVEL MEMORY CELL 审中-公开

    公开(公告)号：US20240321347A1

    公开(公告)日：2024-09-26

    申请号：US18643126

    申请日：2024-04-23

    Applicant: Micron Technology, Inc.

    Inventor： Mattia Robustelli ,  Fabio Pellizzer ,  Innocenzo Tortorelli ,  Agostino Pirovano

    IPC: G11C11/56 ,  G11C7/10

    CPC classification number: G11C11/56 ,  G11C7/1051 ,  G11C7/1096

    Abstract: Methods, systems, and devices for reading a multi-level memory cell are described. The memory cell may be configured to store three or more logic states. The memory device may apply a first read voltage to a memory cell to determine a logic state stored by the memory cell. The memory device may determine whether a first snapback event occurred and apply a second read voltage based on determining that the first snapback event failed to occur based on applying the first read voltage. The memory device may determine whether a second snapback event occurred and determine the logic state based on whether the first snapback event or the second snapback event occurred.

    DECODING ARCHITECTURE FOR MEMORY DEVICES
    78.
    发明公开
    DECODING ARCHITECTURE FOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20240203481A1

    公开(公告)日：2024-06-20

    申请号：US18391368

    申请日：2023-12-20

    Applicant: Micron Technology, Inc.

    Inventor： Paolo Fantini ,  Enrico Varesi ,  Lorenzo Fratin ,  Fabio Pellizzer

    IPC: G11C11/408 ,  G11C5/06 ,  G11C11/4074

    CPC classification number: G11C11/4085 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/4087

    Abstract: Methods, systems, and devices for a decoding architecture for memory devices are described. Word line plates of a memory array may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. Two word line plates in a same plane may be activated via a shared electrode. Memory cells coupled with the two word line plates sharing the electrode, or a subset thereof, may represent a logical page for accessing memory cells. A memory cell may be accessed via a first voltage applied to a word line plate coupled with the memory cell and a second voltage applied to a pillar electrode coupled with the memory cell. Parallel or simultaneous access operations may be performed for two or more memory cells within a same page of memory cells.

    Dirty write on power off
    79.
    发明授权
    Dirty write on power off 有权

    公开(公告)号：US11923007B2

    公开(公告)日：2024-03-05

    申请号：US18049855

    申请日：2022-10-26

    Applicant: Micron Technology, Inc.

    Inventor： Karthik Sarpatwari ,  Fabio Pellizzer ,  Jessica Chen ,  Nevil Gajera

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0038

    Abstract: Methods, systems, and devices for dirty write on power off are described. In an example, the described techniques may include writing memory cells of a device according to one or more parameters (e.g., reset current amplitude), where each memory cell is associated with a storage element storing a value based on a material property associated with the storage element. Additionally, the described techniques may include identifying, after writing the memory cells, an indication of power down for the device and refreshing, before the power down of the device, a portion of the memory cells based on identifying the indication of the power down for the device. In some cases, refreshing includes modifying at least one of the one or more parameters for a write operation for the portion of the memory cells.

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