公开(公告)号：US5893748A

公开(公告)日：1999-04-13

申请号：US799053

申请日：1997-02-10

Applicant: Ming-Ren Lin

Inventor： Ming-Ren Lin

IPC: H01L21/033 ,  H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/0337 ,  H01L21/76816 ,  Y10S438/942 ,  Y10S438/974

Abstract: A method for producing a small feature in a semiconductor device includes depositing a mask material on an unpatterned layer in which an ultra-narrow opening is to be formed, and then masking and etching the mask material to form a narrow opening. A spacer material is then deposited on the mask material, with spacer material settling into and covering the narrow opening. Thereafter, a portion of the spacer material is removed by etching, leaving some spacer material in the opening but exposing an ultra-narrow region of the first layer at the bottom of the opening in the mask material. The ultra-narrow region left uncovered by the spacer material is smaller than the narrow region in the mask material. Once the ultra-narrow region is uncovered, material in the first layer is removed through the ultra-narrow region, by anisotropic etching, for example, to form an ultra-narrow opening in the first layer.

Abstract translation: 一种用于制造半导体器件中的小特征的方法包括：将掩模材料沉积在要形成超窄开口的未图案化层上，然后掩蔽和蚀刻掩模材料以形成窄开口。 然后将间隔物材料沉积在掩模材料上，其中间隔物材料沉降并覆盖窄开口。 此后，通过蚀刻去除间隔物材料的一部分，在开口中留下一些间隔物材料，但在掩模材料的开口底部露出第一层的超窄区域。 由间隔物材料未覆盖的超窄区域比掩模材料中的窄区域小。 一旦超窄区域被覆盖，例如通过各向异性蚀刻在第一层中的材料通过超窄区域去除，以在第一层中形成超窄的开口。

公开(公告)号：US5866473A

公开(公告)日：1999-02-02

申请号：US961853

申请日：1997-10-31

Applicant: Qi Xiang ,  Ming-Ren Lin

Inventor： Qi Xiang ,  Ming-Ren Lin

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L29/66575 ,  H01L21/26506 ,  H01L21/28123 ,  H01L29/42376

Abstract: A method of manufacturing an MOS transistor having a gate length dimension less than the dimension available by methods available with conventional manufacturing methods that are limited by optical diffraction in photolithography. The method includes forming a polysilicon gate structure on a gate oxide layer, forming a nitrogen-doped layer on the polysilicon gate structure, forming selected depth oxide sidewalls on the polysilicon gate structure and etching the nitrogen-doped layer and the oxide sidewalls.

Abstract translation: 一种制造栅极长度尺寸小于通过在光刻中受光学衍射限制的常规制造方法可获得的尺寸的尺寸的MOS晶体管的方法。 该方法包括在栅极氧化物层上形成多晶硅栅极结构，在多晶硅栅极结构上形成氮掺杂层，在多晶硅栅极结构上形成选定的深度氧化物侧壁，并蚀刻氮掺杂层和氧化物侧壁。

公开(公告)号：US5770519A

公开(公告)日：1998-06-23

申请号：US464305

申请日：1995-06-05

Applicant: Richard K. Klein ,  Darrell Erb ,  Steven Avanzino ,  Robin Cheung ,  Scott Luning ,  Bryan Tracy ,  Subhash Gupta ,  Ming-Ren Lin

Inventor： Richard K. Klein ,  Darrell Erb ,  Steven Avanzino ,  Robin Cheung ,  Scott Luning ,  Bryan Tracy ,  Subhash Gupta ,  Ming-Ren Lin

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/4763 ,  H01L21/44

CPC classification number: H01L21/76831 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002

Abstract: A multilayer semiconductor structure includes a conductive via. The conductive via includes a reservoir of metal having a high resistance to electromigration. The reservoir is made from a conformal layer of copper, or gold deposited over the via to form a copper, or gold plug located in the via. A barrier layer is provided between the reservoir and an insulating layer to prevent the reservoir from diffusing into the insulating layer. The barrier layer and reservoir may be deposited by sputtering, collimated sputtering, chemical vapor deposition (CVD), dipping, evaporating, or by other means. The barrier layer and reservoir may be etched by anisotropic dry etching, plasma-assisted etching, or other layer removal techniques.

Abstract translation: 多层半导体结构包括导电通孔。 导电通孔包括具有高抗电迁移性的金属储存器。 储存器由铜的共形层或沉积在通孔上的金形成，以形成位于通孔中的铜或金塞。 在储存器和绝缘层之间设置阻挡层，以防止储存器扩散到绝缘层中。 可以通过溅射，准直溅射，化学气相沉积（CVD），浸渍，蒸发或其它方式沉积阻挡层和储层。 可以通过各向异性干蚀刻，等离子体辅助蚀刻或其它层去除技术来蚀刻阻挡层和储存器。

公开(公告)号：US5753967A

公开(公告)日：1998-05-19

申请号：US800148

申请日：1997-02-13

Applicant: Ming-Ren Lin

Inventor： Ming-Ren Lin

IPC: H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/58 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/76831 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76807 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002

Abstract: Submicron contacts/vias and trenches are provided in a dielectric layer by forming an opening having an initial dimension and reducing the initial dimension by depositing a second dielectric material in the opening.

公开(公告)号：US5686354A

公开(公告)日：1997-11-11

申请号：US478324

申请日：1995-06-07

Applicant: Steven Avanzino ,  Subhash Gupta ,  Rich Klein ,  Scott D. Luning ,  Ming-Ren Lin

Inventor： Steven Avanzino ,  Subhash Gupta ,  Rich Klein ,  Scott D. Luning ,  Ming-Ren Lin

IPC: H01L21/768 ,  H01L21/28

CPC classification number: H01L21/76831 ,  H01L21/76807

Abstract: A dual damascene method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a thin protective via mask to form the via openings. A conductive line mask pattern is used to form conductive line openings in an insulating layer. Next, a thin protective layer of conformal material is deposited in the conducive line opening. The protective layer and the insulating layer each have etch resistance to others etchant. Using a via mask pattern, openings are etching the protective layer with the insulating layer serving as and etch stop. Next via openings are etched in the insulating material using the openings in the thin protective layer as the etch mask. If the protective layer is a conductive material, it is removed from the surface of the insulating layer either before or after the conductive line and via openings are filled with a conductive material. If the protective material is an insulating material, it is entirely removed before filling the conductive line and via openings conductive material.

Abstract translation: 一种双镶嵌方法，用于制造导线的互连级别并且连接用于集成电路的绝缘和用于半导体器件的衬底载体的通孔，其使用薄的保护性通孔掩模形成通孔。 导电线掩模图案用于在绝缘层中形成导电线路开口。 接下来，在导电线路开口中沉积有保形材料的薄保护层。 保护层和绝缘层各自具有对其它蚀刻剂的耐蚀刻性。 使用通孔掩模图案，开口蚀刻保护层，绝缘层用作蚀刻停止。 接下来通过开口被蚀刻在绝缘材料中，使用薄保护层中的开口作为蚀刻掩模。 如果保护层是导电材料，则在导电线之前或之后将其从绝缘层的表面去除，并且通孔开口填充有导电材料。 如果保护材料是绝缘材料，则在填充导电线和通孔开口导电材料之前将其完全去除。

公开(公告)号：US08222680B2

公开(公告)日：2012-07-17

申请号：US10274961

申请日：2002-10-22

Applicant: Ming-Ren Lin ,  Judy Xilin An ,  Zoran Krivokapic ,  Cyrus E. Tabery ,  Haihong Wang ,  Bin Yu

Inventor： Ming-Ren Lin ,  Judy Xilin An ,  Zoran Krivokapic ,  Cyrus E. Tabery ,  Haihong Wang ,  Bin Yu

IPC: H01L29/72

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/66818

Abstract: A double gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin, a first gate and a second gate. The first gate is formed on top of the fin. The second gate surrounds the fin and the first gate. In another implementation, a triple gate MOSFET includes a fin, a first gate, a second gate, and a third gate. The first gate is formed on top of the fin. The second gate is formed adjacent the fin. The third gate is formed adjacent the fin and opposite the second gate.

Abstract translation: 双栅极金属氧化物半导体场效应晶体管（MOSFET）包括鳍状物，第一栅极和第二栅极。 第一个门形成在鳍的顶部。 第二个门围绕翅片和第一个门。 在另一实施方案中，三栅极MOSFET包括鳍片，第一栅极，第二栅极和第三栅极。 第一个门形成在鳍的顶部。 第二个门形成在翅片附近。 第三栅极形成在翅片附近并与第二栅极相对。

公开(公告)号：US07871873B2

公开(公告)日：2011-01-18

申请号：US12413174

申请日：2009-03-27

Applicant: Witold Maszara ,  Ming-Ren Lin ,  Jin Cho ,  Zoran Krivokapic

Inventor： Witold Maszara ,  Ming-Ren Lin ,  Jin Cho ,  Zoran Krivokapic

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/336

CPC classification number: H01L29/66795

Abstract: A method of manufacturing semiconductor fins for a semiconductor device may begin by providing a bulk semiconductor substrate. The method continues by growing a layer of first epitaxial semiconductor material on the bulk semiconductor substrate, and by growing a layer of second epitaxial semiconductor material on the layer of first epitaxial semiconductor material. The method then creates a fin pattern mask on the layer of second epitaxial semiconductor material. The fin pattern mask has features corresponding to a plurality of fins. Next, the method anisotropically etches the layer of second epitaxial semiconductor material, using the fin pattern mask as an etch mask, and using the layer of first epitaxial semiconductor material as an etch stop layer. This etching step results in a plurality of fins formed from the layer of second epitaxial semiconductor material.

Abstract translation: 制造用于半导体器件的半导体鳍片的方法可以通过提供体半导体衬底开始。 该方法通过在体半导体衬底上生长第一外延半导体材料层并通过在第一外延半导体材料层上生长第二外延半导体材料层来继续。 该方法然后在第二外延半导体材料层上产生鳍状图案掩模。 翅片图形掩模具有对应于多个翅片的特征。 接下来，使用鳍图案掩模作为蚀刻掩模，并且使用第一外延半导体材料层作为蚀刻停止层，该方法各向异性地蚀刻第二外延半导体材料的层。 该蚀刻步骤导致由第二外延半导体材料层形成的多个鳍片。

公开(公告)号：US07713834B2

公开(公告)日：2010-05-11

申请号：US12205361

申请日：2008-09-05

Applicant: Haihong Wang ,  Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

Inventor： Haihong Wang ,  Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

IPC: H01L21/76

CPC classification number: H01L21/76224 ,  H01L21/823481 ,  H01L29/1054

Abstract: A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a ALD process.

Abstract translation: 集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。 浅沟槽隔离技术用于应变硅（SMOS）工艺。 用于沟槽的衬垫由半导体或金属层形成，该半导体或金属层在低温过程中沉积，这降低了锗除气。 低温过程可以是ALD过程。

公开(公告)号：US07648886B2

公开(公告)日：2010-01-19

申请号：US10341863

申请日：2003-01-14

Applicant: Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

Inventor： Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

IPC: H01L21/762

CPC classification number: H01L21/76224

Abstract: A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed to in a low temperature process which reduces germanium outgassing. The low temperature process can be a UVO, ALD, CVD, PECVD, or HDP process.

Abstract translation: 集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。 浅沟槽隔离技术用于应变硅（SMOS）工艺。 用于沟槽的衬垫形成为能够减少锗除气的低温过程。 低温过程可以是UVO，ALD，CVD，PECVD或HDP工艺。

公开(公告)号：US07416925B2

公开(公告)日：2008-08-26

申请号：US11677404

申请日：2007-02-21

Applicant: Ming-Ren Lin ,  Bin Yu

Inventor： Ming-Ren Lin ,  Bin Yu

IPC: H01L21/00

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/78687

Abstract: A semiconductor device includes a substrate and an insulating layer on the substrate. The semiconductor device also includes a fin structure formed on the insulating layer, where the fin structure includes first and second side surfaces, a dielectric layer formed on the first and second side surfaces of the fin structure, a first gate electrode formed adjacent the dielectric layer on the first side surface of the fin structure, a second gate electrode formed adjacent the dielectric layer on the second side surface of the fin structure, and a doped structure formed on an upper surface of the fin structure in the channel region of the semiconductor device.

Abstract translation: 半导体器件包括衬底和衬底上的绝缘层。 半导体器件还包括形成在绝缘层上的翅片结构，其中鳍结构包括第一和第二侧表面，形成在鳍结构的第一和第二侧表面上的电介质层，形成在电介质层附近的第一栅电极 在翅片结构的第一侧表面上形成与鳍结构的第二侧表面上的电介质层相邻的第二栅电极，以及在半导体器件的沟道区中形成在鳍结构的上表面上的掺杂结构 。