公开(公告)号：US20050111288A1

公开(公告)日：2005-05-26

申请号：US10762827

申请日：2004-01-21

申请人： Noboru Shibata ,  Tomoharu Tanaka

发明人： Noboru Shibata ,  Tomoharu Tanaka

IPC分类号： G11C16/02 ,  G11C7/00 ,  G11C11/56 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C2211/5621 ,  G11C2211/5642

摘要： For a verify operation using potential Vbi′, the data of a memory cell is preliminarily read by using potential Vai+1 and the state of the memory cell is stored in a latch circuit. Then, a verify/read operation is conducted by using potential Vbi′. If the state of the cell is higher than Ai+1, the outcome of the verify/read operation is forcibly brought down to a low level. Thus, only two latch circuits are required for storing an n-bit data, including one for storing the data to be written and one for preliminarily reading if the state of the cell is higher than Ai+1 or not and storing the outcome of the preliminary reading.

公开(公告)号：US06876578B2

公开(公告)日：2005-04-05

申请号：US10676313

申请日：2003-09-30

申请人： Noboru Shibata ,  Tomoharu Tanaka

发明人： Noboru Shibata ,  Tomoharu Tanaka

IPC分类号： G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/12

CPC分类号： G11C16/3459 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/12 ,  G11C2211/5642 ,  G11C2211/5648

摘要： Before the next data is stored into a first memory cell in which i bits of data have been stored, i or less bits of data are written into cells adjacent to the first memory cell beforehand. The writing of i or less bits of data is done using a threshold voltage lower than the original threshold voltage (or the actual threshold voltage in storing i bits of data). After the adjacent cells have been written into, writing is done to raise the threshold voltage of the first memory cell.

摘要翻译： 在下一个数据被存储到已经存储了i个比特数据的第一存储单元中之前，预先将I或更少的数据位写入与第一存储单元相邻的单元。 使用低于原始阈值电压（或存储i位数据的实际阈值电压）的阈值电压来完成I或更少数据位的写入。 在相邻单元被写入之后，进行写入以提高第一存储单元的阈值电压。

公开(公告)号：US06707719B2

公开(公告)日：2004-03-16

申请号：US10379471

申请日：2003-03-04

申请人： Noboru Shibata ,  Tomoharu Tanaka

发明人： Noboru Shibata ,  Tomoharu Tanaka

IPC分类号： G11C1634

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C2211/5621 ,  G11C2211/5642

摘要： For a verify operation using potential Vbi′, the data of a memory cell is preliminarily read by using potential Vai+1 and the state of the memory cell is stored in a latch circuit. Then, a verify/read operation is conducted by using-potential Vbi′. If the state of the cell is higher than Ai+1, the outcome of the verify/read operation is forcibly brought down to a low level. Thus, only two latch circuits are required for storing an n-bit data, including one for storing the data to be written and one for preliminarily reading if the state of the cell is higher than Ai+1 or not and storing the outcome of the preliminary reading.

摘要翻译： 对于使用电位Vbi'的验证操作，通过使用电位Vai + 1预先读取存储单元的数据，并将存储单元的状态存储在锁存电路中。 然后，通过使用电位Vbi'进行验证/读取操作。 如果单元的状态高于Ai + 1，则验证/读取操作的结果被强制降低到低水平。 因此，只需要两个锁存电路来存储n位数据，包括一个用于存储要写入的数据的数据，一个用于在小区的状态高于Ai + 1时预先读取，并且存储 初步阅读。

公开(公告)号：US06611938B1

公开(公告)日：2003-08-26

申请号：US09604692

申请日：2000-06-27

申请人： Tomoharu Tanaka ,  Noboru Shibata ,  Toru Tanzawa

发明人： Tomoharu Tanaka ,  Noboru Shibata ,  Toru Tanzawa

IPC分类号： H03M1300

CPC分类号： G06F11/10 ,  G06F11/1008 ,  G06F11/1068 ,  G06F11/1072 ,  G11C7/1006 ,  G11C16/0483 ,  G11C16/10 ,  G11C2029/0411 ,  G11C2207/104

摘要： A flash memory comprises a memory sector, a command interface, a first signal buffer, a control signal generation circuit, a control signal generation circuit, a data input buffer, an error correction circuit, an address buffer, an address signal generation circuit, a plurality of data memory circuits, and write means. The command interface receives a write data input instruction from an external device to generate a write data input instruction signal, and receives a write instruction from the external device to generate a write instruction signal. The error correction circuit is activated by the write data input instruction signal to receive the write data in synchronization with the write enable signal, and is activated by the write instruction signal to generate a check data for an error correction in synchronization with the control signal. With this configuration, processing to generate the check data for the error correction with the internal error correction circuit and processing to input the check data to the write circuit, etc. can be automatically performed in the flash memory even in the period when the external control signal is not input.

摘要翻译： 闪速存储器包括存储器扇区，命令接口，第一信号缓冲器，控制信号生成电路，控制信号生成电路，数据输入缓冲器，纠错电路，地址缓冲器，地址信号生成电路 多个数据存储电路和写入装置。 命令接口从外部设备接收写入数据输入指令，生成写入数据输入指令信号，并从外部设备接收写入指令，生成写入指令信号。 误差校正电路由写数据输入指令信号激活，以与写使能信​​号同步地接收写入数据，并由写指令信号激活，以产生与控制信号同步的纠错校验数据。 利用这种配置，即使在外部控制的时间段中也可以在闪速存储器中自动执行利用内部纠错电路生成用于纠错的校验数据的处理和将写入电路等的校验数据输入的处理 信号未输入。

公开(公告)号：US06496412B1

公开(公告)日：2002-12-17

申请号：US10084509

申请日：2002-02-28

申请人： Noboru Shibata ,  Tomoharu Tanaka

发明人： Noboru Shibata ,  Tomoharu Tanaka

IPC分类号： G11C1604

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/26 ,  G11C2211/5621 ,  G11C2211/5642

摘要： A multivalued memory has data of state “0”, state “1”, state “2”, and state “3” whose threshold voltages increase in that order. In a first-page write operation, a memory cell whose data is in state “0” is brought into state “1”. In a second-page write operation, a memory cell whose data is in state “0” is brought into state “3” and a memory cell whose data is in state “1” is brought into state “2”. As a result, in reading the data, the data on the first page can be read in two read operations. Furthermore, the operation of writing the data onto the second page can be made faster, because a high initial write voltage can be used.

摘要翻译： 多值存储器具有状态“0”，状态“1”，状态“2”和阈值电压按照该顺序增加的状态“3”的数据。 在第一页写操作中，数据处于状态“0”的存储单元进入状态“1”。 在第二页写入操作中，数据处于状态“0”的存储单元进入状态“3”，数据处于状态“1”的存储单元进入状态“2”。 结果，在读取数据时，可以在两个读取操作中读取第一页上的数据。 此外，由于可以使用高的初始写入电压，因此可以使得将数据写入第二页的操作更快。

公开(公告)号：US06487122B2

公开(公告)日：2002-11-26

申请号：US10034515

申请日：2001-12-27

申请人： Noboru Shibata ,  Tomoharu Tanaka

发明人： Noboru Shibata ,  Tomoharu Tanaka

IPC分类号： G11C1634

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C2211/5621 ,  G11C2211/5642

摘要： For a verify operation using potential Vbi′, the data of a memory cell is preliminarily read by using potential Vai+1 and the state of the memory cell is stored in a latch circuit. Then, a verify/read operation is conducted by using potential Vbi′. If the state of the cell is higher than Ai+1, the outcome of the verify/read operation is forcibly brought down to a low level. Thus, only two latch circuits are required for storing an n-bit data, including one for storing the data to be written and one for preliminarily reading if the state of the cell is higher than Ai+1 or not and storing the outcome of the preliminary reading.

摘要翻译： 对于使用电位Vbi'的验证操作，通过使用电位Vai + 1预先读取存储单元的数据，并将存储单元的状态存储在锁存电路中。 然后，通过使用电位Vbi'进行验证/读取操作。 如果单元的状态高于Ai + 1，则验证/读取操作的结果被强制降低到低水平。 因此，只需要两个锁存电路来存储n位数据，包括一个用于存储要写入的数据的数据，一个用于在小区的状态高于Ai + 1时预先读取，并且存储 初步阅读。

公开(公告)号：US06426892B2

公开(公告)日：2002-07-30

申请号：US09898032

申请日：2001-07-05

申请人： Noboru Shibata ,  Tomoharu Tanaka

发明人： Noboru Shibata ,  Tomoharu Tanaka

IPC分类号： G11C1604

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/26 ,  G11C2211/5621 ,  G11C2211/5642

摘要： A multivalued memory has data of state “0”, state “1”, state “2”, and state “3” whose threshold voltages increase in that order. In a first-page write operation, a memory cell whose data is in state “0” is brought into state “1”. In a second-page write operation, a memory cell whose data is in state “0” is brought into state “3” and a memory cell whose data is in state “1” is brought into state “2”. As a result, in reading the data, the data on the first page can be read in two read operations. Furthermore, the operation of writing the data onto the second page can be made faster, because a high initial write voltage can be used.

公开(公告)号：US06178115B1

公开(公告)日：2001-01-23

申请号：US09470652

申请日：1999-12-22

申请人： Noboru Shibata ,  Tomoharu Tanaka

发明人： Noboru Shibata ,  Tomoharu Tanaka

IPC分类号： G11C1604

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C2211/5621 ,  G11C2211/5642

摘要： For a verify operation using potential Vbi′, the data of a memory cell is preliminarily read by using potential Vai+1 and the state of the memory cell is stored in a latch circuit. Then, a verify/read operation is conducted by using potential Vbi′. If the state of the cell is higher than Ai+1, the outcome of the verify/read operation is forcibly brought down to a low level. Thus, only two latch circuits are required for storing an n-bit data, including one for storing the data to be written and one for preliminarily reading if the state of the cell is higher than Ai+1 or not and storing the outcome of the preliminary reading.

摘要翻译： 对于使用电位Vbi'的验证操作，通过使用电位Vai + 1预先读取存储单元的数据，并将存储单元的状态存储在锁存电路中。 然后，通过使用电位Vbi'进行验证/读取操作。 如果单元的状态高于Ai + 1，则验证/读取操作的结果被强制降低到低水平。 因此，只需要两个锁存电路来存储n位数据，包括一个用于存储要写入的数据的数据，一个用于在小区的状态高于Ai + 1时预先读取，并且存储 初步阅读。

公开(公告)号：US09042180B2

公开(公告)日：2015-05-26

申请号：US13995166

申请日：2012-03-25

申请人： Toru Tanzawa ,  Tomoharu Tanaka

发明人： Toru Tanzawa ,  Tomoharu Tanaka

IPC分类号： G11C16/30 ,  G11C5/14 ,  G11C29/00

CPC分类号： G06F1/32 ,  G11C5/145 ,  G11C16/30 ,  G11C29/702

摘要： An integrated circuit includes a circuit block to utilize a load current at a load voltage from a power input and two or more charge pump arrays. The outputs of the charge pump arrays are coupled to the power input of the circuit block. The integrated circuit includes one or more modifiable elements to disable one or more of the two or more charge pump arrays.

摘要翻译： 集成电路包括电路块，以利用来自电源输入和两个或更多个电荷泵阵列的负载电压的负载电流。 电荷泵阵列的输出耦合到电路块的功率输入。 集成电路包括一个或多个可修改的元件以禁用两个或更多个电荷泵阵列中的一个或多个。

公开(公告)号：US08964474B2

公开(公告)日：2015-02-24

申请号：US13524872

申请日：2012-06-15

申请人： Midori Morooka ,  Tomoharu Tanaka

发明人： Midori Morooka ,  Tomoharu Tanaka

IPC分类号： G11C16/00

CPC分类号： G11C16/0483 ,  G11C16/06 ,  G11C16/3427 ,  G11C2213/71

摘要： Apparatuses are described that include stacked arrays of memory cell strings and their methods of operation. Apparatuses include architectures that reduce the use of several common components, allowing greater device density and smaller device size for a given semiconductor area.

摘要翻译： 描述了包括存储器单元串的堆叠阵列及其操作方法的装置。 装置包括减少几个常用部件的使用的结构，允许给定半导体区域的更大的器件密度和更小的器件尺寸。