公开(公告)号：US20060280010A1

公开(公告)日：2006-12-14

申请号：US11507576

申请日：2006-08-22

申请人： Satoru Hanzawa ,  Kiyoo Itoh ,  Hideyuki Matsuoka ,  Motoyasu Terao ,  Takeshi Sakata

发明人： Satoru Hanzawa ,  Kiyoo Itoh ,  Hideyuki Matsuoka ,  Motoyasu Terao ,  Takeshi Sakata

IPC分类号： G11C7/00

CPC分类号： H01L27/101 ,  G11C7/12 ,  G11C8/10 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0042 ,  G11C2013/0054 ,  G11C2013/0078 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144

摘要： The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected word line conduct. To achieve the object, a source line parallel to a data line is provided, a precharge circuit for equipotentially driving both and a circuit for selectively driving the source line are arranged. Owing to this configuration, a current path is created in only a cell selected by a row decoder and a column decoder and a read-out signal can be generated. Therefore, a lower-power, lower-noise and more highly integrated nonvolatile memory such as a phase change memory can be realized, compared with a conventional type.

公开(公告)号：US07110284B2

公开(公告)日：2006-09-19

申请号：US10931041

申请日：2004-09-01

申请人： Jun Hayakawa ,  Hideyuki Matsuoka

发明人： Jun Hayakawa ,  Hideyuki Matsuoka

IPC分类号： G11C11/00

CPC分类号： G11C11/16

摘要： A magnetic nonvolatile memory cell includes a C-MOSFET, a spin torque magnetization inversion layer and a tunneling magnetoresistive layer arranged in this order. The memory cell has the function of spin torque magnetization inversion and consumes very low power. A random access memory includes a plurality of the memory cells.

摘要翻译： 磁性非易失性存储单元包括依次布置的C-MOSFET，自旋转矩磁化反转层和隧道磁阻层。 存储单元具有自旋转矩磁化反转的功能，并且消耗非常低的功率。 随机存取存储器包括多个存储单元。

公开(公告)号：US07002831B2

公开(公告)日：2006-02-21

申请号：US10715448

申请日：2003-11-19

申请人： Hideyuki Matsuoka ,  Kenchi Ito ,  Takeshi Sakata ,  Kiyoo Itoh

发明人： Hideyuki Matsuoka ,  Kenchi Ito ,  Takeshi Sakata ,  Kiyoo Itoh

IPC分类号： G11C17/02

CPC分类号： G11C11/16

摘要： A memory cell in a so-called MRAM by utilizing a tunnel magnetic resistance in the prior art has raised problems that a magnetic field to be applied to a TMR element is essentially weak since a word line for write is disposed apart from the TMR element, that a large current is required at the time of a writing operation, and that electric power consumption is large. In order to solve the above-described problems experienced in the prior art, the present invention provides an MRAM memory cell structure and its fabricating method in which a word line for write is disposed near a TMR element and surrounds it in three directions.

摘要翻译： 通过利用现有技术中的隧道磁阻，在所谓的MRAM中的存储单元已经引起了由于用于写入的字线与TMR元件分开而被施加到TMR元件的磁场基本上是弱的问题， 在写入操作时需要大的电流，并且电力消耗大。 为了解决现有技术中遇到的上述问题，本发明提供了一种MRAM存储单元结构及其制造方法，其中用于写入的字线被设置在TMR元件附近并且在三个方向上包围它。

公开(公告)号：US06965533B2

公开(公告)日：2005-11-15

申请号：US11037090

申请日：2005-01-19

申请人： Takeshi Sakata ,  Hideyuki Matsuoka

发明人： Takeshi Sakata ,  Hideyuki Matsuoka

IPC分类号： G11C13/00 ,  G11C7/10 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L43/08 ,  G11C7/00

CPC分类号： G11C7/1096 ,  G11C7/1006 ,  G11C7/1078 ,  G11C11/1673 ,  G11C11/1675

摘要： A write operation of a MRAM in which a current necessary for inverting magnetization of an MTJ element has to be passed through a data line and therefore current consumption is large. The write operation comprises: comparing input data DI with read data GO read from a memory cell array and encoding the input data DI to form write data GI by a data encoder WC; and decoding the read data GO by a data decoder RD to form output data DO. In a nonvolatile semiconductor memory in which the current is passed through the data line to write data into a memory cell, the number of bits to be written during the write operation is reduced, and the current consumption can be reduced. This can realize the MRAM including a low-power highly-integrated memory.

摘要翻译： MRAM的写入操作，其中必须使MTJ元件的磁化反转所必需的电流通过数据线，因此电流消耗大。 写入操作包括：将输入数据DI与从存储单元阵列读取的读取数据GO进行比较，并且通过数据编码器WC对输入数据DI进行编码以形成写入数据GI; 以及通过数据解码器RD对读取的数据GO进行解码以形成输出数据DO。 在其中电流通过数据线将数据写入存储单元的非易失性半导体存储器中，在写入操作期间要写入的位数减少，并且可以减少电流消耗。 这可以实现包括低功率高度集成的存储器的MRAM。

公开(公告)号：US20050128835A1

公开(公告)日：2005-06-16

申请号：US11037090

申请日：2005-01-19

申请人： Takeshi Sakata ,  Hideyuki Matsuoka

发明人： Takeshi Sakata ,  Hideyuki Matsuoka

IPC分类号： G11C13/00 ,  G11C7/10 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L43/08 ,  G11C7/00

CPC分类号： G11C7/1096 ,  G11C7/1006 ,  G11C7/1078 ,  G11C11/1673 ,  G11C11/1675

摘要： A write operation of a MRAM in which a current necessary for inverting magnetization of an MTJ element has to be passed through a data line and therefore current consumption is large. The write operation comprises: comparing input data DI with read data GO read from a memory cell array and encoding the input data DI to form write data GI by a data encoder WC; and decoding the read data GO by a data decoder RD to form output data DO. In a nonvolatile semiconductor memory in which the current is passed through the data line to write data into a memory cell, the number of bits to be written during the write operation is reduced, and the current consumption can be reduced. This can realize the MRAM including a low-power highly-integrated memory.

公开(公告)号：US06862235B2

公开(公告)日：2005-03-01

申请号：US10373959

申请日：2003-02-27

申请人： Takeshi Sakata ,  Hideyuki Matsuoka

发明人： Takeshi Sakata ,  Hideyuki Matsuoka

IPC分类号： G11C13/00 ,  G11C7/10 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L43/08 ,  G11C7/00

CPC分类号： G11C7/1096 ,  G11C7/1006 ,  G11C7/1078 ,  G11C11/1673 ,  G11C11/1675

摘要： There is disclosed a write operation of a MRAM in which a current necessary for inverting magnetization of an MTJ element has to be passed through a data line and therefore current consumption is large. The write operation comprises: comparing input data DI with read data GO read from a memory cell array and encoding the input data DI to form write data GI by a data encoder WC; and decoding the read data GO by a data decoder RD to form output data DO. In a nonvolatile semiconductor memory in which the current is passed through the data line to write data into a memory cell, the number of bits to be written during the write operation is reduced, and the current consumption can be reduced. This can realize the MRAM including a low-power highly-integrated memory.

摘要翻译： 公开了一种MRAM的写入操作，其中必须使MTJ元件的磁化反转所需的电流通过数据线，因此电流消耗大。 写入操作包括：将输入数据DI与从存储单元阵列读取的读取数据GO进行比较，并且通过数据编码器WC对输入数据DI进行编码以形成写入数据GI; 以及通过数据解码器RD对读取的数据GO进行解码以形成输出数据DO。 在其中电流通过数据线将数据写入存储单元的非易失性半导体存储器中，在写入操作期间要写入的位数减少，并且可以减少电流消耗。 这可以实现包括低功率高度集成的存储器的MRAM。

公开(公告)号：US06740921B2

公开(公告)日：2004-05-25

申请号：US10307373

申请日：2002-12-02

申请人： Hideyuki Matsuoka ,  Kiyoo Itoh ,  Motoyasu Terao ,  Satoru Hanzawa ,  Takeshi Sakata

发明人： Hideyuki Matsuoka ,  Kiyoo Itoh ,  Motoyasu Terao ,  Satoru Hanzawa ,  Takeshi Sakata

IPC分类号： H01L27108

CPC分类号： H01L27/2454 ,  G11C13/0004 ,  G11C2213/79 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

摘要： A semiconductor memory cell and forming method thereof utilizes a vertical select transistor to eliminate the problem of a large cell surface area in memory cells of the related art utilizing phase changes. A memory cell with a smaller surface area than the DRAM device of the related art is achieved by the present invention. Besides low power consumption during read operation, the invention also provides phase change memory having low power consumption even during write operation. Phase change memory also has stable read-out operation.

公开(公告)号：US07719870B2

公开(公告)日：2010-05-18

申请号：US11976532

申请日：2007-10-25

申请人： Satoru Hanzawa ,  Kiyoo Itoh ,  Hideyuki Matsuoka ,  Motoyasu Terao ,  Takeshi Sakata

发明人： Satoru Hanzawa ,  Kiyoo Itoh ,  Hideyuki Matsuoka ,  Motoyasu Terao ,  Takeshi Sakata

IPC分类号： G11C7/00

CPC分类号： H01L27/101 ,  G11C7/12 ,  G11C8/10 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0042 ,  G11C2013/0054 ,  G11C2013/0078 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144

摘要： The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected wordline conduct. To achieve the object, a source line parallel to a data line is provided, a precharge circuit for equipotentially driving both and a circuit for selectively driving the source line are arranged. Owing to this configuration, a current path is created in only a cell selected by a row decoder and a column decoder and a read-out signal can be generated. Therefore, a lower-power, lower-noise and more highly integrated nonvolatile memory such as a phase change memory can be realized, compared with a conventional type.

摘要翻译： 本发明的目的是避免在由选择的字线上的所有存储单元中的选择晶体管导通的存储单元中构成的存储器阵列中的未选择的数据线被驱动，每个存储器单元使用依赖于可变电阻的存储元件和选择晶体管 。 为了实现该目的，提供了与数据线并行的源极线，布置用于等电位驱动两者的预充电电路和用于选择性地驱动源极线的电路。 由于该配置，仅在由行解码器选择的单元中创建电流路径，并且可以生成列解码器，并且可以生成读出信号。 因此，与常规型相比，可以实现诸如相变存储器的低功率，低噪声和更高度集成的非易失性存储器。

公开(公告)号：US07341892B2

公开(公告)日：2008-03-11

申请号：US11368603

申请日：2006-03-07

申请人： Hideyuki Matsuoka ,  Kiyoo Itoh ,  Motoyasu Terao ,  Satoru Hanzawa ,  Takeshi Sakata

发明人： Hideyuki Matsuoka ,  Kiyoo Itoh ,  Motoyasu Terao ,  Satoru Hanzawa ,  Takeshi Sakata

IPC分类号： H01L21/82

CPC分类号： H01L27/2454 ,  G11C13/0004 ,  G11C2213/79 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

摘要： A semiconductor memory cell and forming method thereof utilizes a vertical select transistor to eliminate the problem of a large cell surface area in memory cells of the related art utilizing phase changes. A memory cell with a smaller surface area than the DRAM device of the related art is achieved by the present invention. Besides low power consumption during read operation, the invention also provides phase change memory having low power consumption even during write operation. Phase change memory also has stable read-out operation.

公开(公告)号：US07116593B2

公开(公告)日：2006-10-03

申请号：US10485566

申请日：2002-09-13

申请人： Satoru Hanzawa ,  Kiyoo Itoh ,  Hideyuki Matsuoka ,  Motoyasu Terao ,  Takeshi Sakata

发明人： Satoru Hanzawa ,  Kiyoo Itoh ,  Hideyuki Matsuoka ,  Motoyasu Terao ,  Takeshi Sakata

IPC分类号： G11C7/00

CPC分类号： H01L27/101 ,  G11C7/12 ,  G11C8/10 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0042 ,  G11C2013/0054 ,  G11C2013/0078 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144

摘要： The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected word line conduct. To achieve the object, a source line parallel to a data line is provided, a precharge circuit for equipotentially driving both and a circuit for selectively driving the source line are arranged. Owing to this configuration, a current path is created in only a cell selected by a row decoder and a column decoder and a read-out signal can be generated. Therefore, a lower-power, lower-noise and more highly integrated nonvolatile memory such as a phase change memory can be realized, compared with a conventional type.

摘要翻译： 本发明的目的是避免在由存储单元组成的存储器阵列中驱动未选择的数据线，每个存储器单元在选择的字线上的所有存储单元中的选择晶体管时，根据可变电阻使用存储元件和选择晶体管 进行。 为了实现该目的，提供了与数据线并行的源极线，布置用于等电位驱动两者的预充电电路和用于选择性地驱动源极线的电路。 由于该配置，仅在由行解码器选择的单元中创建电流路径，并且可以生成列解码器，并且可以生成读出信号。 因此，与常规型相比，可以实现诸如相变存储器的低功率，低噪声和更高度集成的非易失性存储器。