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    Circuit and method for image artifact reduction in high-density, highpixel-count, image sensor with phase detection autofocus
    72.
    发明授权
    Circuit and method for image artifact reduction in high-density, highpixel-count, image sensor with phase detection autofocus 有权

    公开(公告)号：US11683604B1

    公开(公告)日：2023-06-20

    申请号：US17678533

    申请日：2022-02-23

    Applicant: OmniVision Technologies, Inc.

    Inventor： Liang Zuo ,  Rui Wang ,  Selcuk Sen ,  Xuelian Liu ,  Min Qu ,  Hiroaki Ebihara

    IPC: H04N25/704 ,  H04N25/11 ,  H04N25/60

    CPC classification number: H04N25/704 ,  H04N25/11 ,  H04N25/60

    Abstract: An image sensor includes an array of multiple-photodiode cells, each photodiode coupled through a selection transistor to a floating diffusion of the cell, the selection transistors controlled by respective transfer lines, a reset, a sense source follower, and a read transistor coupled from the source follower to a data line. The array includes phase detection rows with phase detection cells and normal cells; and a compensation row of more cells. In embodiments, each phase detection row has cells with at least one photodiode coupled to the floating diffusion by selection transistors controlled by a transfer line separate from transfer lines of selection transistors of adjacent normal cells of the row. In embodiments, the compensation row has cells with photodiodes coupled to the floating diffusion by selection transistors controlled by a transfer line separate from transfer lines of selection transistors of adjacent normal cells of the compensation row.

    Image sensor with three readout approach for phase detection autofocus and image sensing photodiodes through multiple column bitlines
    74.
    发明授权
    Image sensor with three readout approach for phase detection autofocus and image sensing photodiodes through multiple column bitlines 有权

    公开(公告)号：US11463648B1

    公开(公告)日：2022-10-04

    申请号：US17342375

    申请日：2021-06-08

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Chengcheng Xu ,  Rui Wang ,  Wei Deng ,  Chun-Sheng Yang ,  Xueqing Wang

    IPC: H04N5/378 ,  H04N5/232 ,  H04N5/374 ,  H04N5/369

    Abstract: An imaging device includes a photodiode array with a first and second photodiodes. First and second floating diffusions are configured to receive charge from the first and second photodiodes, respectively. An analog to digital converter (ADC) is configured to receive simultaneously first and second bitline signals from the first and second floating diffusions, respectively. The ADC is configured to generate a reference readout in response to the first and second bitline signals after a reset operation. The ADC next generates a first half of a phase detection autofocus (PDAF) readout in response to the first and second bitline signals after charge is transferred from the first PDAF photodiode to the first floating diffusion. The ADC then generates a full image readout in response to the first and second bitline signals after charge is transferred from the second photodiode to the second floating diffusion.

    Image sensor with shifted color filter array pattern and bit line pairs
    75.
    发明授权
    Image sensor with shifted color filter array pattern and bit line pairs 有权

    公开(公告)号：US11284045B2

    公开(公告)日：2022-03-22

    申请号：US16855857

    申请日：2020-04-22

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Qingfei Chen ,  Rui Wang ,  Wei Wei Wang ,  Zhiyong Zhan ,  Xin Wang ,  Qingwei Shan ,  Kenny Geng

    IPC: H04N5/374 ,  H04N9/04 ,  H04N5/369 ,  H04N5/378 ,  H04N5/3745 ,  H01L27/146

    Abstract: An imaging device includes groupings of photodiodes having four photodiodes. A transfer transistor is between each photodiode and a floating diffusion. Each floating diffusion is coupled to up to two photodiodes per grouping at a time through transfer transistors. A buffer transistor is coupled to each floating diffusion. The buffer transistors may be in a first or second grouping of buffer transistors. A first bit line is coupled to up to two buffer transistors of the first grouping and a second bit line is coupled to up to two buffer transistors of the second grouping of buffer transistors at a time. A color filter array including a plurality of groupings of color filters is disposed over respective photodiodes of the photodiode array, wherein each grouping of color filters includes four color filters having a same color, wherein each grouping of color filters overlaps two groupings of photodiodes.

    Image sensor with capacitor randomization for column gain
    76.
    发明授权
    Image sensor with capacitor randomization for column gain 有权

    公开(公告)号：US11240458B2

    公开(公告)日：2022-02-01

    申请号：US16900576

    申请日：2020-06-12

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Hiroaki Ebihara ,  Rui Wang ,  John Brummer ,  Shan Chen

    IPC: H04N5/378 ,  H04N5/365 ,  H04N5/355

    Abstract: A pixel cell readout circuit includes a bitline input stage coupled to a bitline to receive an image signal from a pixel cell. A capacitor ratio circuit is coupled to the bitline input stage. A gain of the bitline input stage is responsive to a capacitor ratio provided by the capacitor ratio circuit to the bitline input stage. A switch control circuit is coupled to receive a gain signal. The switch control circuit is coupled to generate a randomized pattern selection signal coupled to be received by the capacitor ratio circuit to select the capacitor ratio provided by the capacitor ratio circuit in response to the gain signal.

    Image sensor with frame level black level calibration
    77.
    发明授权
    Image sensor with frame level black level calibration 有权

    公开(公告)号：US11206392B1

    公开(公告)日：2021-12-21

    申请号：US16931194

    申请日：2020-07-16

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Liang Zuo ,  Min Qu ,  Xuelian Liu ,  Rui Wang ,  Zhe Gao ,  Zhiyong Zhan

    IPC: H04N17/00 ,  H04N5/3745 ,  H04N5/378

    Abstract: An image sensor includes a pixel array with active rows of pixel cells, a black level calibration row with black image data generation circuits coupled to generate black image data signals representative of an absence of the incident light, and a dummy row with black level clamping circuits coupled to receive a black sun reference voltage to clamp bitlines of the pixel array, and a black level calibration circuit coupled to receive the black sun reference voltage to generate a black sun calibration voltage. A black sun feedback circuit is coupled to generate the black sun reference voltage in response to the black sun calibration voltage and a black level sample reference, and a black level sampling circuit is coupled to the bitlines to sample the black image data signals to generate the black level sample reference received by the black sun feedback circuit.

    DUAL ROW SELECT PIXEL FOR FAST PIXEL BINNING
    78.
    发明申请
    DUAL ROW SELECT PIXEL FOR FAST PIXEL BINNING 有权

    公开(公告)号：US20210360175A1

    公开(公告)日：2021-11-18

    申请号：US17066200

    申请日：2020-10-08

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Tiejun Dai ,  Hiroaki Ebihara ,  Sang Joo Lee ,  Rui Wang ,  Hiroki Ui

    IPC: H04N5/347 ,  H04N5/378 ,  H04N9/04

    Abstract: A pixel array includes pixel cells, each including photodiodes. A source follower is coupled to generate an image signal in response image charge generated by the photodiodes. A first row select transistor is coupled to the source follower to output the image signal of the pixel cell. Pixel cells are organized into columns including a first column and a second column. The first row select transistors of the pixel cells of the first and second columns of pixel cells are coupled to first and second column bitlines, respectively. The pixel cells of the second column of pixel cells further include a second row select transistor coupled to the source follower to output the respective image signal to the first column bitline.

    Circuit and method for control of counter start time
    79.
    发明授权
    Circuit and method for control of counter start time 有权

    公开(公告)号：US11128307B2

    公开(公告)日：2021-09-21

    申请号：US16175586

    申请日：2018-10-30

    Applicant: OmniVision Technologies, Inc.

    Inventor： Rui Wang ,  Yu-Shen Yang ,  Shan Chen ,  Min Qu

    IPC: H03M1/00 ,  H03M1/06 ,  H04N5/361 ,  H04N5/376 ,  H04N5/369 ,  H04N5/378

    Abstract: An analog to digital conversion (ADC) circuit includes a ramp circuit coupled to output a ramp signal, and the ramp signal is offset from a starting voltage by an offset voltage. The ramp signal ramps towards the starting voltage. A counter circuit is coupled to the ramp circuit to start counting after the ramp signal returns to the starting voltage, and a comparator is coupled to the counter circuit and a bitline to compare the ramp signal to a pixel signal voltage on the bitline. In response to the ramp signal equaling the pixel signal voltage, the comparator stops the counter.

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