公开(公告)号：US06218857B1

公开(公告)日：2001-04-17

申请号：US09198796

申请日：1998-11-24

申请人： Bradley A. Sharpe-Geisler ,  Giap Tran

发明人： Bradley A. Sharpe-Geisler ,  Giap Tran

IPC分类号： H03K19177

CPC分类号： H03K19/17744 ,  H03K19/09429 ,  H03K19/1778

摘要： An input/output block (IOB) in a field programmable gate array (FPGA) efficiently provides signals to an inter-connect network in the FPGA device. The IOB is one of a plurality of IOBs positioned about a plurality of variable grain blocks (VGBs) in the FPGA device. The IOB includes a first sized line driving amplifier for generating a first signal at a first IOB output. A second sized line driving amplifier generates a second signal at a second IOB output. The first sized line driving amplifier includes a PMOS transistor having a polysilicon gate width of approximately 20 microns and an NMOS transistor having a polysilicon gate width of approximately 10 microns. The second sized line driving amplifier includes a PMOS transistor, an NMOS transistor, a NAND gate, NOR gate and inverter. The second sized amplifier PMOS transistor has a polysilicon gate width of approximately 35 microns and an NMOS transistor having a polysilicon gate width of approximately 15 microns. The IOB has multiple outputs connected to various inter-connect network resources. An IOB output is coupled to a (1) direct connect line, (2) NOR line, (3) dendrite line and (4) MaxL line. The various lines may have a predetermined length and/or capacitance. The various sized amplifiers in the IOB are sized dependent upon the respective line types connected to the IOB. The various sized amplifiers allow for the reduction of undue signal propagation delays or unnecessarily large sized amplifiers.

摘要翻译： 现场可编程门阵列（FPGA）中的输入/输出块（IOB）有效地向FPGA器件中的互连网络提供信号。 IOB是围绕FPGA器件中的多个可变粒子块（VGB）定位的多个IOB之一。 IOB包括用于在第一IOB输出处产生第一信号的第一尺寸线驱动放大器。 第二尺寸线驱动放大器在第二IOB输出端产生第二信号。 第一尺寸线驱动放大器包括具有约20微米的多晶硅栅极宽度的PMOS晶体管和具有约10微米的多晶硅栅极宽度的NMOS晶体管。 第二尺寸线驱动放大器包括PMOS晶体管，NMOS晶体管，NAND门，NOR门和反相器。 第二尺寸放大器PMOS晶体管具有大约35微米的多晶硅栅极宽度和具有约15微米的多晶硅栅极宽度的NMOS晶体管。 IOB具有连接到各种互连网络资源的多个输出。 IOB输出耦合到（1）直接连接线，（2）NOR线，（3）枝晶线和（4）MaxL线。 各种线可以具有预定的长度和/或电容。 IOB中的各种尺寸的放大器的大小取决于连接到IOB的各种线路类型。 各种尺寸的放大器允许减少不适当的信号传播延迟或不必要的大尺寸放大器。

公开(公告)号：US6124733A

公开(公告)日：2000-09-26

申请号：US996442

申请日：1997-12-22

申请人： Bradley A. Sharpe-Geisler

发明人： Bradley A. Sharpe-Geisler

IPC分类号： H03K3/3565 ,  H03K19/003 ,  H03B1/00 ,  H03K3/037 ,  H03K19/0175

CPC分类号： H03K3/3565

摘要： An input buffer includes a first CMOS inverter (400) made up of a PMOS transistor (602) connecting Vdd to the buffer output and an NMOS transistor (604) connecting the buffer output to Vss. NMOS transistors (404) and (414) have with series connected source to drain paths to connect the buffer output to Vss in conjunction with transistor (604) of inverter (400). PMOS transistors (402) and (412) have series connected source to drain paths connecting Vdd to the buffer output in conjunction with transistor (602). To control transistors (402, 404, 412 and 414) an inverter (420) is connected from the buffer output to the gates of transistors (402 and 404), and inverters (431, 432, 433, and 440) are connected between the buffer input and the gates of transistors (412 and 414). After a low to high buffer input transition above a level (H1), the inverter (420) will transition and the NMOS transistors (404 and 414) will turn on together to create a path to Vss with transistor (604) of inverter (400) to decrease the buffer threshold to (H2). After the buffer input rises further above a threshold (H1A) of inverter (431) combined with inverter (440), inverter (433) will turn off transistor (414) to set the buffer threshold back to (H1). After a high to low buffer input transition below a level (H1), the inverter (420) will transition and the PMOS transistors (402 and 412) will both be on together to create a path to Vdd with transistor (602) of inverter (400) to increase the buffer threshold to (H3). After the buffer input falls further below a threshold (H1B) of inverters (431) and (440), inverter (433) will turn off transistor (412) to set the buffer threshold back to (H1).

摘要翻译： 输入缓冲器包括由将Vdd连接到缓冲器输出的PMOS晶体管（602）和将缓冲器输出连接到Vss的NMOS晶体管（604）构成的第一CMOS反相器（400）。 NMOS晶体管（404）和（414）具有串联连接的源极到漏极路径，以将缓冲器输出连接到逆变器（400）的晶体管（604）。 PMOS晶体管（402）和（412）具有串联连接的源至漏极路径，连接Vdd与晶体管（602）的缓冲器输出。 为了控制晶体管（402,404,412和414），逆变器（420）从缓冲器输出连接到晶体管（402和404）的栅极，并且反相器（431,432,433和440）连接在晶体管 缓冲器输入和晶体管（412和414）的栅极。 在高于电平（H1）的低至高缓冲器输入转换之后，反相器（420）将转变，并且NMOS晶体管（404和414）将一起导通以产生到Vss的路径，其中逆变器（400）的晶体管（604） ）将缓冲器阈值降低到（H2）。 在缓冲器输入进一步升高到与逆变器（440）组合的逆变器（431）的阈值（H1A）之上，反相器（433）将关闭晶体管（414）以将缓冲器阈值设置为（H1）。 在低电平（H1）的高到低的缓冲器输入转换之后，反相器（420）将转变，并且PMOS晶体管（402和412）将两者都在一起，以产生与变换器晶体管（602）的Vdd的路径 400）将缓冲区阈值增加到（H3）。 在缓冲器输入进一步低于反相器（431）和（440）的阈值（H1B）之后，反相器（433）将关闭晶体管（412）以将缓冲器阈值设置为（H1）。

公开(公告)号：US6072351A

公开(公告)日：2000-06-06

申请号：US912763

申请日：1997-08-18

申请人： Bradley A. Sharpe-Geisler

发明人： Bradley A. Sharpe-Geisler

IPC分类号： H03K19/003 ,  H03K5/08

CPC分类号： H03K19/00315

摘要： An output buffer including transistors which tolerate a maximum gate to source, gate to drain, or drain to source voltage ("the maximum tolerable voltage"), such as 2.7 volts, the transistors being configured to produce an output voltage significantly higher than the maximum tolerable voltage. The output buffer includes pull up transistors having source to drain paths connected in series to connect a voltage supply higher than the maximum tolerable voltage to the buffer output. The buffer further includes pull down transistors having source to drain paths connected in series to connect the buffer output to ground. The buffer further includes power supply circuitry to apply gate voltages to the pull up and pull down transistors so that the voltage potential from the source to drain of each of the pull up and pull down transistors is less than the maximum tolerable voltage. The power supply circuitry further controls gate voltages so that neither the gate to source, nor the gate to drain voltage for each of the pull up and pull down transistors exceeds the maximum tolerable voltage. Additionally, the power supply circuitry is itself configured so that voltage across the gate to source, gate to drain, or source to drain for each of its transistors does not exceed the maximum tolerable voltage. The power supply circuitry further provides a tristate configuration so that voltages can be applied to the buffer output from an external source exceeding the maximum tolerable voltage without a voltage from the gate to source, gate to drain, or source to drain of a transistor in the output buffer exceeding the maximum tolerable voltage.

摘要翻译： 输出缓冲器包括容纳最大栅极至源极，栅极至漏极或漏极至源极电压（“最大可容忍电压”）的晶体管，例如2.7伏，晶体管被配置为产生明显高于最大值的输出电压 耐受电压 输出缓冲器包括具有串联连接的源极至漏极路径的上拉晶体管，以将高于最大容许电压的电压源连接到缓冲器输出端。 该缓冲器还包括具有串联连接的源极至漏极路径的下拉晶体管，以将缓冲器输出端连接到地。 缓冲器还包括电源电路，以将栅极电压施加到上拉和下拉晶体管，使得每个上拉和下拉晶体管的源极到漏极的电压电位小于最大容许电压。 电源电路还控制栅极电压，使得每个上拉和下拉晶体管的栅极到源极以及栅极到漏极电压都不超过最大容许电压。 此外，电源电路本身被配置成使得栅极到源极，栅极到漏极或者其晶体管的每个晶体管的源极到漏极之间的电压不超过最大容许电压。 电源电路还提供三态配置，使得电压可以从超过最大容许电压的外部源施加到缓冲器输出，而没有电压从栅极到源极，栅极到漏极或源极到漏极中的晶体管的电压 输出缓冲器超过最大容许电压。

公开(公告)号：US5912550A

公开(公告)日：1999-06-15

申请号：US196080

申请日：1998-11-19

申请人： Bradley A. Sharpe-Geisler

发明人： Bradley A. Sharpe-Geisler

IPC分类号： G05F1/575 ,  G05F3/26 ,  G05F1/56

CPC分类号： G05F1/575 ,  G05F3/262

摘要： A power converter provides a voltage reference (Vdd) to a plurality of transistors on an integrated circuit with a limited voltage swing when a load is connected and removed. The power converter includes an opamp (100) having an input (+) receiving a voltage reference (V.sub.DIOD), an input (-) connected to a resistor divider (102, 104) and an output driving the gate of a transistor (110). The transistor (110) has a source to drain path providing a 3.3 volt supply (NV3EXT) to an output node (n2) which supplies Vdd. The output node (n2) is connected back to the resistor divider (102,104) and to the source of a cascode transistor (300). The cascode (300) is connected with cascode (302) to form a current mirror which is interconnected with transistor (304) and capacitor (306) to slow the response at node (n7) to transitions at the output node (n2). Cascode (300) drives a current mirror (314, 316). The operational amplifier (100) functions to control the gate voltage of transistor (110) to maintain the voltage Vdd at a constant value. With significant loading to the output, after the loading is removed, cascode (300) will turn on to cause transistor (316) to limit the voltage swing of Vdd until opamp (100) can return Vdd to a constant value.

摘要翻译： 当负载被连接和移除时，功率转换器在集成电路上具有有限的电压摆幅的多个晶体管提供电压基准（Vdd）。 功率转换器包括具有接收电压参考（VDIOD）的输入（+）的运算放大器（100），连接到电阻分压器（102,104）的输入（ - ）和驱动晶体管（110）的栅极的输出， 。 晶体管（110）具有向提供Vdd的输出节点（n2）提供3.3伏电源（NV3EXT）的源极到漏极路径。 输出节点（n2）连接回电阻分压器（102,104）并连接到共源共栅晶体管（300）的源极。 共源共栅（300）与共源共栅（302）连接以形成与晶体管（304）和电容器（306）互连的电流镜，以将节点（n7）处的响应减慢到输出节点（n2）处的转变。 Cascode（300）驱动电流镜（314,316）。 运算放大器（100）用于控制晶体管（110）的栅极电压以将电压Vdd维持在恒定值。 随着对输出的显着负载，在去除负载之后，共源共栅（300）将导通，以使晶体管（316）限制Vdd的电压摆幅，直到运算放大器（100）可以将Vdd返回到恒定值。

公开(公告)号：US5760609A

公开(公告)日：1998-06-02

申请号：US666193

申请日：1996-06-19

申请人： Bradley A. Sharpe-Geisler

发明人： Bradley A. Sharpe-Geisler

IPC分类号： H03K3/037 ,  H03K3/356 ,  H03K19/177 ,  H03K19/21 ,  H03K19/00

CPC分类号： H03K19/1774 ,  H03K19/17704 ,  H03K19/1778 ,  H03K19/215 ,  H03K3/037 ,  H03K3/0375 ,  H03K3/356156

摘要： A clock signal providing circuit with enable and pulse generator with enable for use in a block clock circuit of a programmable logic device (PLD), the block clock circuit for allocating multiple clock signals to each macrocell of the PLD. The clock signal providing circuit includes circuitry which functions to change states in response to a pin clock signal when an enable signal is active, and to maintain its current state when the enable signal is inactive. The pulse generator includes circuitry which functions to provide a pulse at a first edge of a pin clock signal if an enable signal remains active from prior to receipt of the first edge of the pin clock signal.

摘要翻译： 一种具有使能和脉冲发生器的时钟信号提供电路，其可用于可编程逻辑器件（PLD）的块时钟电路中，块时钟电路用于向PLD的每个宏单元分配多个时钟信号。 时钟信号提供电路包括当使能信号有效时响应于引脚时钟信号而改变状态的电路，并且当使能信号无效时保持其当前状态。 脉冲发生器包括用于在引脚时钟信号的第一边缘处提供脉冲的电路，如果使能信号在接收到引脚时钟信号的第一沿之前保持有效。

公开(公告)号：US5723984A

公开(公告)日：1998-03-03

申请号：US659279

申请日：1996-06-06

申请人： Bradley A. Sharpe-Geisler

发明人： Bradley A. Sharpe-Geisler

IPC分类号： H03K19/177 ,  H03K19/173

CPC分类号： H03K19/17748 ,  H03K19/17704 ,  H03K19/17736

摘要： A method of programing an FPGA to enable encoding of configuration logic block (CLB) outputs enabling an efficient use of FPGA routing resources. The method of the present invention utilizes the one hot approach, wherein only one CLB output is high at a time, to form a state machine using an FPGA. To provide encoding, programmable interconnect points (PIPs) may be programmed to connect CLB outputs to interconnect lines so that the interconnect lines indicate states of the CLB outputs in an encoded form. To provide such encoding, less interconnect lines than CLB outputs provide the encoded form of the CLB outputs. Thus, PIPs can connect a single interconnect line to more than one CLB output. Further, PIPs can connect a single CLB output to interconnect lines provided in separate parallel routing paths. To prevent erroneous results, CLB outputs which are not hot are tri-stated. Output decoding can be provided by an additional decoder in the FPGA connected to the interconnect lines providing the encoded form of the CLB outputs. Output decoding may alternatively be provided using a CLB.

摘要翻译： FPGA的编程方法，能够对配置逻辑块（CLB）输出进行编码，从而有效利用FPGA路由资源。 本发明的方法利用一种热法，其中一次只有一个CLB输出为高，以形成使用FPGA的状态机。 为了提供编码，可编程可编程互连点（PIP）以将CLB输出连接到互连线，使得互连线以编码形式指示CLB输出的状态。 为了提供这样的编码，比CLB输出更少的互连线提供CLB输出的编码形式。 因此，PIP可以将单个互连线连接到多个CLB输出。 此外，PIP可以将单个CLB输出连接到在单独的并行路由路径中提供的互连线。 为了防止错误的结果，不是很热的CLB输出是三态的。 输出解码可以通过连接到互连线的FPGA中的附加解码器来提供CLB输出的编码形式。 也可以使用CLB提供输出解码。

公开(公告)号：US5668488A

公开(公告)日：1997-09-16

申请号：US341636

申请日：1994-11-17

申请人： Bradley A. Sharpe-Geisler ,  Fabiano Fontana

发明人： Bradley A. Sharpe-Geisler ,  Fabiano Fontana

IPC分类号： H03K19/00 ,  H03K19/003 ,  H03K19/084

CPC分类号： H03K19/00323 ,  H03K19/0027

摘要： An input buffer which provides compensation for the RC time delay introduced by a switch matrix of a high density programmable logic device (PLD). The input buffer includes circuitry to provide an input threshold which varies to compensate for the RC delay of the switch matrix to produce an output which transitions when a signal input to the switch matrix transitions through a predetermined value.

摘要翻译： 输入缓冲器，用于对由高密度可编程逻辑器件（PLD）的开关矩阵引入的RC时间延迟进行补偿。 输入缓冲器包括提供输入阈值的电路，其变化以补偿开关矩阵的RC延迟，以产生当输入到开关矩阵的信号转变为预定值时转变的输出。

公开(公告)号：US5638018A

公开(公告)日：1997-06-10

申请号：US459786

申请日：1995-06-02

申请人： Bradley A. Sharpe-Geisler

发明人： Bradley A. Sharpe-Geisler

IPC分类号： H03K3/356

CPC分类号： H03K3/35606 ,  H03K3/356156

摘要： A P-type flip-flop, which selectively functions in a D-type flip-flop mode or latch mode depending on its clock signal input. The P-type flip-flop has an output changing states to follow its data input at a leading edge of its clock input, the output then does not change states for a period .epsilon., and then the output changing states to match its data input after the period .epsilon. if a signal is received at its clock input having a period greater than .epsilon.. With a pulse applied at the clock input having a width less than .epsilon., the P-type flip-flop is edge sensitive functioning similar to a D-type flip-flop. With a pulse with longer than .epsilon. applied to the clock input, the P-type flip-flop appears transparent similar to a latch.

摘要翻译： P型触发器，其选择性地根据其时钟信号输入在D型触发器模式或锁存模式中起作用。 P型触发器具有在其时钟输入的前沿跟随其数据输入的输出改变状态，然后输出不改变周期ε的状态，然后输出改变状态以匹配其之后的数据输入 如果在其时钟输入处接收到具有大于ε的周期的信号的周期ε。 通过在时钟输入端施加的脉冲具有小于ε的宽度，P型触发器的边缘敏感功能类似于D型触发器。 使用长于ε的脉冲施加到时钟输入，P型触发器似乎与锁存器相似。

公开(公告)号：US5406139A

公开(公告)日：1995-04-11

申请号：US34510

申请日：1993-03-19

申请人： Bradley A. Sharpe-Geisler

发明人： Bradley A. Sharpe-Geisler

IPC分类号： H03K19/0175 ,  H03K19/00 ,  H03K19/017 ,  H03K19/0185 ,  H03K17/10

CPC分类号： H03K19/018521 ,  H03K19/0016 ,  H03K19/01721

摘要： An input buffer for utilization in a programmable logic device (PLD). The input buffer includes an inverter consisting of a PMOS pull up transistor one half the size of a corresponding NMOS pull down transistor to enable TTL compatibility. To drive a high capacitance load, instead of utilizing further buffering which introduces gate delays, a cascode transistor is used to control an additional pull up output driver connected to the output of the inverter. The cascode functions to turn on the additional pull up output driver to supplement the PMOS pull up transistor during a low to high transition of the output. The input buffer further includes a switching transistor coupled between a V.sub.DD power supply and the PMOS pull up transistor to cut power to the PMOS pull up transistor when the inverter has a low output. With no utilization of power during a low output, the input buffer provides a zero power TTL input enabling the input buffer to be utilized on circuitry in battery powered devices.

摘要翻译： 用于可编程逻辑器件（PLD）的输入缓冲器。 输入缓冲器包括一个由PMOS上拉晶体管组成的反相器，其大小为相应的NMOS下拉晶体管的一半，以实现TTL兼容性。 为了驱动高电容负载，代替利用引入栅极延迟的进一步的缓冲，使用共源共栅晶体管来控制连接到逆变器的输出的附加上拉输出驱动器。 串联功能用于打开附加上拉输出驱动器，以在输出的低到高转换期间补充PMOS上拉晶体管。 输入缓冲器还包括耦合在VDD电源和PMOS上拉晶体管之间的开关晶体管，以在反相器具有低输出时切断PMOS上拉晶体管的功率。 在低输出时不使用电源，输入缓冲器提供零功率TTL输入，使输入缓冲器能够在电池供电的设备的电路上使用。

公开(公告)号：US06720755B1

公开(公告)日：2004-04-13

申请号：US10146734

申请日：2002-05-16

申请人： Bradley A. Sharpe-Geisler

发明人： Bradley A. Sharpe-Geisler

IPC分类号： G05F316

CPC分类号： G05F3/30

摘要： A band gap reference includes circuitry providing a reference voltage (VDIODE) at 1.0 volt or below to provide a stable reference for 1.3 volt or lower circuits, which would otherwise not function accurately with a typical band gap reference of 1.2 volts. The band gap reference includes an op-amp equally driving the gate of various current source transistors. A first current source drives a BJT transistor connected in a diode fashion, while a second current source drives a further diode connected BJT transistor through a resistor. An output VDIODE is provided from a further resistor connected to two additional current sources. The first of these current sources is driven by the op-amp output to increase output with temperature, while the second of these current sources is driven by a replicating op-amp connected to a resistor providing current decreasing with temperature, both current sources functioning to provide a stable low voltage VDIODE on the resistor with variations in temperature and supply voltage.

摘要翻译： 带隙基准包括提供1.0伏特或更低电压的参考电压（VDIODE）的电路，为1.3伏特或更低电路提供稳定的参考电压，否则电压将不能用1.2伏的典型带隙基准精确地运行。 带隙基准包括一个均等地驱动各种电流源晶体管的栅极的运算放大器。 第一电流源驱动以二极管方式连接的BJT晶体管，而第二电流源通过电阻驱动另一个连接的BJT晶体管的二极管。 输出VDIODE由连接到两个附加电流源的另一电阻器提供。 这些电流源中的第一个由运算放大器输出驱动，以通过温度增加输出，而第二个电流源由连接到电阻器的复制运算放大器驱动，提供电流随温度的降低，两个电流源均起作用 在电阻上提供稳定的低电压VDIODE，温度和电源电压变化。