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71.发明授权Method for shallow trench isolated, contacted well, vertical MOSFET DRAM 失效浅沟槽隔离方法，接触良好，垂直MOSFET DRAM公开(公告)号：US06284593B1
公开(公告)日：2001-09-04
申请号：US09705652
申请日：2000-11-03
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/10867
摘要： A process of forming a hybrid memory cell which is scalable to a minimum feature size, F, of about 60 nm at an operating voltage of Vblh of about 1.5 V and substantially free of floating-well effects is provided.
摘要翻译： 提供了形成混合存储器单元的过程，该混合存储器单元在约1.5V的Vblh的工作电压下可扩展到约60nm的最小特征尺寸F，并且基本上没有浮动阱效应。
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72.发明授权公开(公告)号：US06281064B1
公开(公告)日：2001-08-28
申请号：US09325941
申请日：1999-06-04
IPC分类号： H01L218238
CPC分类号： H01L21/823842 , H01L27/10873 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： A method for providing dual work function doping and borderless array diffusion contacts includes providing a semiconductor substrate, a gate insulator, a conductor on the gate insulator, an insulating cap on the conductor and insulating spacers on sidewalls of a portion of the conductor and the insulating cap. The method also includes doping portions of the semiconductor substrate and the conductor with a first conductive type and other portions with a second conductive type. The conductor may be annealed such that dopants of the first and second conductive types spread over the respective conductors.
摘要翻译： 一种用于提供双工作功能掺杂和无边界阵列扩散接触的方法包括提供半导体衬底，栅极绝缘体，栅极绝缘体上的导体，导体上的绝缘帽和导体的一部分的侧壁上的绝缘衬垫和绝缘 帽。 该方法还包括以第一导电类型和具有第二导电类型的其它部分掺杂半导体衬底和导体的部分。 导体可以退火，使得第一和第二导电类型的掺杂物分布在相应的导体上。
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73.发明授权Method of forming buried-strap with reduced outdiffusion including removing a sacrificial insulator leaving a gap and supporting spacer 失效一种形成掩埋带的方法，其具有减小的扩散，包括去除留下间隙的牺牲绝缘体和支撑间隔物公开(公告)号：US06242310B1
公开(公告)日：2001-06-05
申请号：US09255534
申请日：1999-02-22
IPC分类号： H01L21336
CPC分类号： H01L27/10867
摘要： A method and structure for forming an integrated circuit memory device includes forming a trench conductor in a trench, forming an isolation collar along a perimeter of an upper portion of the trench conductor, forming supporting spacers above the isolation collar, forming a sacrificial layer between the supporting spacers along an upper surface of the trench conductor, forming an insulator above the sacrificial layer, forming a gate conductor above the insulator, removing the sacrificial layer to form a gap between the insulator and the trench conductor, wherein the supporting spacers maintain a relative position of the gate conductor, the insulator and the trench conductor and forming a conductive strap in the gap.
摘要翻译： 用于形成集成电路存储器件的方法和结构包括在沟槽中形成沟槽导体，沿着沟槽导体的上部的周边形成隔离环，在隔离套环的上方形成支撑隔板，在隔离环之间形成牺牲层 沿着沟槽导体的上表面支撑间隔物，在牺牲层之上形成绝缘体，在绝缘体上方形成栅极导体，去除牺牲层以在绝缘体和沟槽导体之间形成间隙，其中支撑间隔件保持相对 栅极导体，绝缘体和沟槽导体的位置，并在间隙中形成导电带。
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74.发明授权SOI field effect transistor with a back gate for modulating a floating body 失效具有用于调制浮体的背栅的SOI场效应晶体管公开(公告)号：US07772649B2
公开(公告)日：2010-08-10
申请号：US12036325
申请日：2008-02-25
申请人： Kangguo Cheng , Louis C. Hsu , Jack A. Mandelman , Carl Radens , William Tonti
发明人： Kangguo Cheng , Louis C. Hsu , Jack A. Mandelman , Carl Radens , William Tonti
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/66772 , H01L29/78612 , H01L29/78648
摘要： A masking layer is applied over a top semiconductor layer and patterned to expose in an opening a shallow trench isolation structure and a portion of a top semiconductor region within which a first source/drain region and a body is to be formed. Ions are implanted into a portion of a buried insulator layer within the area of the opening to form damaged buried insulator region. The shallow trench isolation structure is removed and the damaged buried insulator region is etched selective to undamaged buried insulator portions to form a cavity. A dielectric layer is formed on the sidewalls and the exposed bottom surface of the top semiconductor region and a back gate filling the cavity is formed. A contact is formed to provide an electrical bias to the back gate so that the electrical potential of the body and the first source/drain region is electrically modulated.
摘要翻译： 将掩模层施加在顶部半导体层上并且被图案化以在开口中暴露浅沟槽隔离结构以及要在其中形成第一源极/漏极区域和主体的顶部半导体区域的一部分。 将离子注入到开口区域内的埋入绝缘体层的一部分中以形成损坏的埋层绝缘体区域。 去除浅沟槽隔离结构，并且损坏的埋层绝缘体区域被选择性地蚀刻到未损坏的埋入绝缘体部分以形成空腔。 在顶部半导体区域的侧壁和暴露的底表面上形成介电层，并且形成填充空腔的背栅。 形成接触以向后栅极提供电偏压，使得主体和第一源极/漏极区域的电势被电调制。
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公开(公告)号：US06548358B2
公开(公告)日：2003-04-15
申请号：US09769494
申请日：2001-01-26
IPC分类号： H01L21336
CPC分类号： H01L23/62 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor fuse is positioned between conductors for connecting wiring lines. The fuse comprises spacers positioned on adjacent ones of the conductors, and a fuse element positioned between the spacers and connected to the wiring lines. A space between the conductors comprises a first width comprising a smallest possible photolithographic width and the fuse element has a second width smaller than the first width.
摘要翻译： 半导体保险丝位于用于连接布线的导体之间。 保险丝包括位于相邻导体上的间隔物，以及定位在间隔件之间并连接到布线的熔丝元件。 导体之间的空间包括包含尽可能小的光刻宽度的第一宽度，并且熔丝元件具有小于第一宽度的第二宽度。
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公开(公告)号：US06258689B1
公开(公告)日：2001-07-10
申请号：US09626328
申请日：2000-07-26
申请人： Gary B. Bronner , Jeffrey P. Gambino , Jack A. Mandelman , Rick L. Mohler , Carl Radens , William R. Tonti
发明人： Gary B. Bronner , Jeffrey P. Gambino , Jack A. Mandelman , Rick L. Mohler , Carl Radens , William R. Tonti
IPC分类号： H01L2120
CPC分类号： H01L27/10861 , H01L29/66181
摘要： Trench capacitors are fabricated utilizing a method which results in a metallic nitride as a portion of a node electrode in a lower region of the trench. The metallic nitride-containing trench electrode exhibits reduced series resistance compared to conventional trench electrodes of similar dimensions, thereby enabling reduced ground rule memory cell layouts and/or reduced cell access time. The trench capacitors of the invention are especially useful as components of DRAM memory cells having various trench configuration and design.
摘要翻译： 使用导致在沟槽的下部区域中作为节点电极的一部分的金属氮化物的方法来制造沟槽电容器。 与具有类似尺寸的常规沟槽电极相比，含金属氮化物的沟槽电极显示出降低的串联电阻，从而能够减少接地规则存储器单元布局和/或降低的单元访问时间。 本发明的沟槽电容器特别可用作具有各种沟槽结构和设计的DRAM存储单元的组件。
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公开(公告)号：US06265279B1
公开(公告)日：2001-07-24
申请号：US09404906
申请日：1999-09-24
申请人： Carl Radens , Jack A. Mandelman , Joachim Hoepfner
发明人： Carl Radens , Jack A. Mandelman , Joachim Hoepfner
IPC分类号： H01L2120
CPC分类号： H01L27/10861 , H01L27/10867 , H01L29/945
摘要： A trench capacitor, in accordance with the present invention, includes a trench formed in a substrate. The trench has a buried plate formed adjacent to a lower portion of the trench. A dielectric collar is formed along vertical sidewalls of the trench. A node diffusion region is formed adjacent to the trench for connecting to a storage node in the trench. A dopant region is formed laterally outward from the trench and adjacent to the collar, and the dopant region includes a profile having a lower portion extending further laterally outward from the trench than an upper portion of the profile wherein operation of a parasitic transistor formed adjacent to the trench between the node diffusion and the buried plate is disrupted by the dopant region. Methods for forming the dopant region are also disclosed and claimed.
摘要翻译： 根据本发明的沟槽电容器包括形成在衬底中的沟槽。 沟槽具有邻近沟槽下部形成的掩埋板。 沿着沟槽的垂直侧壁形成介电环。 在沟槽附近形成节点扩散区域，以连接到沟槽中的存储节点。 掺杂剂区域从沟槽横向向外形成并且与套环相邻，并且掺杂剂区域包括轮廓，该轮廓具有比轮廓的上部更远离沟槽进一步横向向外延伸的轮廓，其中形成为邻近 节点扩散和掩埋板之间的沟槽被掺杂剂区域破坏。 还公开并要求保护形成掺杂剂区域的方法。
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78.发明申请SOI FIELD EFFECT TRANSISTOR WITH A BACK GATE FOR MODULATING A FLOATING BODY 失效具有用于调制浮动体的后盖的SOI场效应晶体管公开(公告)号：US20090212362A1
公开(公告)日：2009-08-27
申请号：US12036325
申请日：2008-02-25
申请人： Kangguo Cheng , Louis C. Hsu , Jack A. Mandelman , Carl Radens , William Tonti
发明人： Kangguo Cheng , Louis C. Hsu , Jack A. Mandelman , Carl Radens , William Tonti
IPC分类号： H01L21/84 , H01L29/786
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/66772 , H01L29/78612 , H01L29/78648
摘要： A masking layer is applied over a top semiconductor layer and patterned to expose in an opening a shallow trench isolation structure and a portion of a top semiconductor region within which a first source/drain region and a body is to be formed. Ions are implanted into a portion of a buried insulator layer within the area of the opening to form damaged buried insulator region. The shallow trench isolation structure is removed and the damaged buried insulator region is etched selective to undamaged buried insulator portions to form a cavity. A dielectric layer is formed on the sidewalls and the exposed bottom surface of the top semiconductor region and a back gate filling the cavity is formed. A contact is formed to provide an electrical bias to the back gate so that the electrical potential of the body and the first source/drain region is electrically modulated.
摘要翻译： 将掩模层施加在顶部半导体层上并且被图案化以在开口中暴露浅沟槽隔离结构以及要在其中形成第一源极/漏极区域和主体的顶部半导体区域的一部分。 将离子注入到开口区域内的埋入绝缘体层的一部分中以形成损坏的埋层绝缘体区域。 去除浅沟槽隔离结构，并且损坏的埋层绝缘体区域被选择性地蚀刻到未损坏的埋入绝缘体部分以形成空腔。 在顶部半导体区域的侧壁和暴露的底表面上形成介电层，并且形成填充空腔的背栅。 形成接触以向后栅极提供电偏压，使得主体和第一源极/漏极区域的电势被电调制。
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公开(公告)号：US06686637B1
公开(公告)日：2004-02-03
申请号：US10301436
申请日：2002-11-21
IPC分类号： H01L2978
CPC分类号： H01L29/66545 , H01L21/26586 , H01L21/28035 , H01L21/28044 , H01L29/1083 , H01L29/4925 , H01L29/665
摘要： A gate structure for a semiconductor transistor is disclosed. In an exemplary embodiment, the gate structure includes a lower polysilicon region doped at a first dopant concentration and an upper polysilicon region doped at a second concentration, with the second concentration being different than the first concentration. A conductive barrier layer is disposed between the lower and the upper polysilicon regions, wherein the conductive barrier layer prevents diffusion of impurities between the lower and the upper polysilicon regions.
摘要翻译： 公开了一种用于半导体晶体管的栅极结构。 在示例性实施例中，栅极结构包括以第一掺杂剂浓度掺杂的下多晶硅区域和以第二浓度掺杂的上多晶硅区域，其中第二浓度不同于第一浓度。 导电阻挡层设置在下部和上部多晶硅区域之间，其中导电阻挡层防止杂质在下部和上部多晶硅区域之间的扩散。
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80.发明授权Semiconductor device utilizing alignment marks for globally aligning the front and back sides of a semiconductor substrate 有权半导体器件利用对准标记来全面对准半导体衬底的正面和背面公开(公告)号：US06617702B2
公开(公告)日：2003-09-09
申请号：US09769080
申请日：2001-01-25
IPC分类号： H01L23544
CPC分类号： H01L23/48 , H01L21/8221 , H01L23/544 , H01L24/48 , H01L24/73 , H01L27/0694 , H01L2223/54473 , H01L2224/05599 , H01L2224/16225 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/73257 , H01L2224/85399 , H01L2924/00014 , H01L2924/01039 , H01L2924/01077 , H01L2924/12041 , H01L2924/12042 , H01L2924/14 , Y10T29/49133 , Y10T29/49155 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： The present invention provides for globally aligning microelectronic circuit systems, such as communication devices and chips, fabricated on or bonded to the front and back sides of one or more substrates to provide for wireless communications between the circuit systems through the one or more substrates. In one embodiment, two circuit systems situated on opposite sides of a substrate are aligned to provide for wireless communications between the two circuit systems through the substrate. In another embodiment, communication devices situated on one or more substrates are aligned to provide for wireless communications between the communication devices through the one or more substrates. In another embodiment, two chips situated on opposite sides of a transparent substrate are aligned to provide for wireless communications between the two chips through the transparent substrate.
摘要翻译： 本发明提供了在一个或多个基板的正面和背面上制造或结合到其上的微电子电路系统，例如通信设备和芯片，以提供通过一个或多个基板的电路系统之间的无线通信。 在一个实施例中，位于衬底的相对侧上的两个电路系统被对准以提供通过衬底的两个电路系统之间的无线通信。 在另一个实施例中，位于一个或多个基板上的通信设备被对准以通过一个或多个基板来提供通信设备之间的无线通信。 在另一个实施例中，位于透明基板的相对侧上的两个芯片被对准以提供通过透明基板的两个芯片之间的无线通信。
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