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387 条记录 (耗时 0.022 秒)

    Method for fabricating a trench capacitor
    1.
    发明授权
    Method for fabricating a trench capacitor 失效
    沟槽电容器的制造方法

    公开(公告)号：US06265279B1

    公开(公告)日：2001-07-24

    申请号：US09404906

    申请日：1999-09-24

    申请人： Carl Radens ,  Jack A. Mandelman ,  Joachim Hoepfner

    发明人： Carl Radens ,  Jack A. Mandelman ,  Joachim Hoepfner

    IPC分类号： H01L2120

    CPC分类号： H01L27/10861 ,  H01L27/10867 ,  H01L29/945

    摘要： A trench capacitor, in accordance with the present invention, includes a trench formed in a substrate. The trench has a buried plate formed adjacent to a lower portion of the trench. A dielectric collar is formed along vertical sidewalls of the trench. A node diffusion region is formed adjacent to the trench for connecting to a storage node in the trench. A dopant region is formed laterally outward from the trench and adjacent to the collar, and the dopant region includes a profile having a lower portion extending further laterally outward from the trench than an upper portion of the profile wherein operation of a parasitic transistor formed adjacent to the trench between the node diffusion and the buried plate is disrupted by the dopant region. Methods for forming the dopant region are also disclosed and claimed.

    摘要翻译： 根据本发明的沟槽电容器包括形成在衬底中的沟槽。 沟槽具有邻近沟槽下部形成的掩埋板。 沿着沟槽的垂直侧壁形成介电环。 在沟槽附近形成节点扩散区域，以连接到沟槽中的存储节点。 掺杂剂区域从沟槽横向向外形成并且与套环相邻，并且掺杂剂区域包括轮廓，该轮廓具有比轮廓的上部更远离沟槽进一步横向向外延伸的轮廓，其中形成为邻近 节点扩散和掩埋板之间的沟槽被掺杂剂区域破坏。 还公开并要求保护形成掺杂剂区域的方法。

    SOI field effect transistor with a back gate for modulating a floating body
    2.
    发明授权
    SOI field effect transistor with a back gate for modulating a floating body 失效
    具有用于调制浮体的背栅的SOI场效应晶体管

    公开(公告)号：US07772649B2

    公开(公告)日：2010-08-10

    申请号：US12036325

    申请日：2008-02-25

    申请人： Kangguo Cheng ,  Louis C. Hsu ,  Jack A. Mandelman ,  Carl Radens ,  William Tonti

    发明人： Kangguo Cheng ,  Louis C. Hsu ,  Jack A. Mandelman ,  Carl Radens ,  William Tonti

    IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

    CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78648

    摘要： A masking layer is applied over a top semiconductor layer and patterned to expose in an opening a shallow trench isolation structure and a portion of a top semiconductor region within which a first source/drain region and a body is to be formed. Ions are implanted into a portion of a buried insulator layer within the area of the opening to form damaged buried insulator region. The shallow trench isolation structure is removed and the damaged buried insulator region is etched selective to undamaged buried insulator portions to form a cavity. A dielectric layer is formed on the sidewalls and the exposed bottom surface of the top semiconductor region and a back gate filling the cavity is formed. A contact is formed to provide an electrical bias to the back gate so that the electrical potential of the body and the first source/drain region is electrically modulated.

    摘要翻译： 将掩模层施加在顶部半导体层上并且被图案化以在开口中暴露浅沟槽隔离结构以及要在其中形成第一源极/漏极区域和主体的顶部半导体区域的一部分。 将离子注入到开口区域内的埋入绝缘体层的一部分中以形成损坏的埋层绝缘体区域。 去除浅沟槽隔离结构，并且损坏的埋层绝缘体区域被选择性地蚀刻到未损坏的埋入绝缘体部分以形成空腔。 在顶部半导体区域的侧壁和暴露的底表面上形成介电层，并且形成填充空腔的背栅。 形成接触以向后栅极提供电偏压，使得主体和第一源极/漏极区域的电势被电调制。

    Low resistance fill for deep trench capacitor
    4.
    发明授权
    Low resistance fill for deep trench capacitor 失效
    深沟槽电容器的低电阻填充

    公开(公告)号：US06258689B1

    公开(公告)日：2001-07-10

    申请号：US09626328

    申请日：2000-07-26

    申请人： Gary B. Bronner ,  Jeffrey P. Gambino ,  Jack A. Mandelman ,  Rick L. Mohler ,  Carl Radens ,  William R. Tonti

    发明人： Gary B. Bronner ,  Jeffrey P. Gambino ,  Jack A. Mandelman ,  Rick L. Mohler ,  Carl Radens ,  William R. Tonti

    IPC分类号： H01L2120

    CPC分类号： H01L27/10861 ,  H01L29/66181

    摘要： Trench capacitors are fabricated utilizing a method which results in a metallic nitride as a portion of a node electrode in a lower region of the trench. The metallic nitride-containing trench electrode exhibits reduced series resistance compared to conventional trench electrodes of similar dimensions, thereby enabling reduced ground rule memory cell layouts and/or reduced cell access time. The trench capacitors of the invention are especially useful as components of DRAM memory cells having various trench configuration and design.

    摘要翻译： 使用导致在沟槽的下部区域中作为节点电极的一部分的金属氮化物的方法来制造沟槽电容器。 与具有类似尺寸的常规沟槽电极相比，含金属氮化物的沟槽电极显示出降低的串联电阻，从而能够减少接地规则存储器单元布局和/或降低的单元访问时间。 本发明的沟槽电容器特别可用作具有各种沟槽结构和设计的DRAM存储单元的组件。

    Field-shield-trench isolation for gigabit DRAMs
    5.
    发明授权
    Field-shield-trench isolation for gigabit DRAMs 有权
    用于千兆位DRAM的场屏蔽沟槽隔离

    公开(公告)号：US06762447B1

    公开(公告)日：2004-07-13

    申请号：US09245269

    申请日：1999-02-05

    申请人： Jack A. Mandelman ,  Rama Divakaruni ,  Giuseppe Larosa ,  Ulrike Gruening ,  Carl Radens

    发明人： Jack A. Mandelman ,  Rama Divakaruni ,  Giuseppe Larosa ,  Ulrike Gruening ,  Carl Radens

    IPC分类号： H01L27108

    CPC分类号： H01L27/10861 ,  H01L21/763 ,  H01L21/765 ,  H01L27/10829 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A dynamic random access memory (DRAM) formed in a semiconductor body has individual pairs of memory cells that are isolated from one another by a vertical electrical isolation trench and are isolated from support circuitry. The isolation trench has sidewalls and upper and lower portions, and encircles an area of the semiconductor body which contains the memory cells. This electrically isolates pairs of memory cells from each other and from the support circuitry contained within the semiconductor body but not located within the encircled area. The lower portion of the isolation trench is filled with an electrically conductive material that has sidewall portions thereof which are at least partly separated from the sidewalls of the lower portion of the trench by a first electrical insulator, and that has a lower portion that is in electrical contact with the semiconductor body. The upper portion of the isolation trench is filled with a second electrical insulator.

    摘要翻译： 形成在半导体主体中的动态随机存取存储器（DRAM）具有通过垂直电隔离沟槽彼此隔离并且与支持电路隔离的各对存储单元。 隔离沟槽具有侧壁和上部和下部，并且包围包含存储单元的半导体主体的区域。 这使得存储器单元对彼此和从包含在半导体本体内但不位于包围区域内的支撑电路电隔离。 隔离沟槽的下部填充有导电材料，该导电材料具有其侧壁部分，其侧壁部分通过第一电绝缘体至少部分地与沟槽的下部的侧壁分离，并且其具有位于 与半导体本体电接触。 隔离沟槽的上部填充有第二电绝缘体。

    Trench field shield in trench isolation
    6.
    发明授权
    Trench field shield in trench isolation 失效
    沟槽隔离屏蔽沟槽

    公开(公告)号：US06420749B1

    公开(公告)日：2002-07-16

    申请号：US09602427

    申请日：2000-06-23

    申请人： Ramachandra Divakaruni ,  Jeffrey P. Gambino ,  Edward W. Kiewra ,  Jack A. Mandelman ,  Carl Radens ,  William R. Tonti

    发明人： Ramachandra Divakaruni ,  Jeffrey P. Gambino ,  Edward W. Kiewra ,  Jack A. Mandelman ,  Carl Radens ,  William R. Tonti

    IPC分类号： H01L27108

    CPC分类号： H01L21/823481 ,  H01L21/743 ,  H01L21/76232 ,  H01L21/76895 ,  H01L21/823475 ,  H01L27/10897

    摘要： A method and structure for a semiconductor device which includes a substrate comprising trenches, a plurality of devices on the substrate isolated by the trenches, conductive sidewall spacers within the trenches, and an insulator filling the trenches between the conductive sidewall spacers. A first conductive sidewall spacer is electrically connected to a first device of said plurality of devices and a second conductive sidewall spacer is electrically connected to a second device of the plurality of devices. The first device can be biased independently of the second device. A contact extends above a surface of the substrate. A first contact abuts a first device and a first conductive sidewall spacer. An insulator separates the conductive sidewall spacers. A first contact may be equidistant between the first conductor and the second conductor. The conductive sidewall spacers comprise field shields.

    摘要翻译： 一种用于半导体器件的方法和结构，其包括：衬底，其包括沟槽，在衬底上隔离的衬底上的多个器件，沟槽内的导电侧壁间隔物，以及填充导电侧壁间隔物之间​​的沟槽的绝缘体。 第一导电侧壁间隔件电连接到所述多个器件中的第一器件，并且第二导电侧壁间隔件电连接到多个器件中的第二器件。 第一装置可以独立于第二装置而被偏置。 接触件在衬底的表面上方延伸。 第一接触件邻接第一器件和第一导电侧壁间隔物。 绝缘体将导电侧墙隔离开。 第一接触件可以在第一导体和第二导体之间等距。 导电侧壁间隔件包括场屏蔽。

    SOI FIELD EFFECT TRANSISTOR WITH A BACK GATE FOR MODULATING A FLOATING BODY
    7.
    发明申请
    SOI FIELD EFFECT TRANSISTOR WITH A BACK GATE FOR MODULATING A FLOATING BODY 失效
    具有用于调制浮动体的后盖的SOI场效应晶体管

    公开(公告)号：US20090212362A1

    公开(公告)日：2009-08-27

    申请号：US12036325

    申请日：2008-02-25

    申请人： Kangguo Cheng ,  Louis C. Hsu ,  Jack A. Mandelman ,  Carl Radens ,  William Tonti

    发明人： Kangguo Cheng ,  Louis C. Hsu ,  Jack A. Mandelman ,  Carl Radens ,  William Tonti

    IPC分类号： H01L21/84 ,  H01L29/786

    CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78648

    摘要： A masking layer is applied over a top semiconductor layer and patterned to expose in an opening a shallow trench isolation structure and a portion of a top semiconductor region within which a first source/drain region and a body is to be formed. Ions are implanted into a portion of a buried insulator layer within the area of the opening to form damaged buried insulator region. The shallow trench isolation structure is removed and the damaged buried insulator region is etched selective to undamaged buried insulator portions to form a cavity. A dielectric layer is formed on the sidewalls and the exposed bottom surface of the top semiconductor region and a back gate filling the cavity is formed. A contact is formed to provide an electrical bias to the back gate so that the electrical potential of the body and the first source/drain region is electrically modulated.

    摘要翻译： 将掩模层施加在顶部半导体层上并且被图案化以在开口中暴露浅沟槽隔离结构以及要在其中形成第一源极/漏极区域和主体的顶部半导体区域的一部分。 将离子注入到开口区域内的埋入绝缘体层的一部分中以形成损坏的埋层绝缘体区域。 去除浅沟槽隔离结构，并且损坏的埋层绝缘体区域被选择性地蚀刻到未损坏的埋入绝缘体部分以形成空腔。 在顶部半导体区域的侧壁和暴露的底表面上形成介电层，并且形成填充空腔的背栅。 形成接触以向后栅极提供电偏压，使得主体和第一源极/漏极区域的电势被电调制。