-
公开(公告)号：US10074747B2
公开(公告)日：2018-09-11
申请号：US15372493
申请日：2016-12-08
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Shunpei Yamazaki , Jun Koyama , Hiroyuki Miyake , Kei Takahashi , Kouhei Toyotaka , Masashi Tsubuku , Kosei Noda , Hideaki Kuwabara
IPC: H01L29/78 , H01L29/786 , H01L23/66 , H01L29/24 , H01L27/088 , H01L29/66 , H01L21/8236 , G06K19/077 , G11C7/00 , G11C19/28 , H02M3/07
CPC classification number: H01L29/78609 , G06K19/07758 , G11C7/00 , G11C19/28 , H01L21/8236 , H01L23/66 , H01L27/0883 , H01L27/1225 , H01L29/24 , H01L29/26 , H01L29/66969 , H01L29/7869 , H01L29/78696 , H01L2223/6677 , H02M3/07
Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.
-
公开(公告)号：US20180145275A1
公开(公告)日：2018-05-24
申请号：US15824644
申请日：2017-11-28
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Shunpei Yamazaki , Satoshi Seo , Hideaki Kuwabara
CPC classification number: H01L51/5209 , G01J1/4228 , H01L25/167 , H01L27/3206 , H01L27/3211 , H01L27/322 , H01L27/3244 , H01L27/3246 , H01L27/3258 , H01L27/3262 , H01L27/3276 , H01L33/0041 , H01L51/0096 , H01L51/5206 , H01L51/5218 , H01L51/5221 , H01L51/5234 , H01L51/524 , H01L51/5271 , H01L51/529 , H01L51/56 , H01L2227/323 , H01L2251/5315
Abstract: A FET is formed on a semiconductor substrate, a curved surface having a radius of curvature is formed on an upper end of an insulation, a portion of a first electrode is exposed corresponding to the curved surface to form an inclined surface, and a region defining a luminescent region is subjected to etching to expose the first electrode. Luminescence emitted from an organic chemical compound layer is reflected by the inclined surface of the first electrode to increase a total quantity of luminescence taken out in a certain direction.
-
公开(公告)号：US20180138211A1
公开(公告)日：2018-05-17
申请号：US15726691
申请日：2017-10-06
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Shunpei Yamazaki , Hiroki Ohara , Toshinari Sasaki , Kosei Noda , Hideaki Kuwabara
IPC: H01L27/12 , H01L29/786 , H01L29/51 , H01L29/24 , G02F1/1333 , G02F1/1368 , G02F1/1362 , G02F1/1343 , G02F1/1337
CPC classification number: H01L27/1225 , G02F1/133345 , G02F1/1337 , G02F1/134309 , G02F1/136227 , G02F1/136277 , G02F1/1368 , H01L27/1214 , H01L27/124 , H01L27/1248 , H01L29/24 , H01L29/517 , H01L29/78609 , H01L29/7869
Abstract: An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.
-
公开(公告)号：US09831459B2
公开(公告)日：2017-11-28
申请号：US15172765
申请日：2016-06-03
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Shunpei Yamazaki , Satoshi Seo , Hideaki Kuwabara
CPC classification number: H01L51/5209 , G01J1/4228 , H01L25/167 , H01L27/3206 , H01L27/3211 , H01L27/322 , H01L27/3244 , H01L27/3246 , H01L27/3258 , H01L27/3262 , H01L27/3276 , H01L33/0041 , H01L51/0096 , H01L51/5206 , H01L51/5218 , H01L51/5221 , H01L51/5234 , H01L51/524 , H01L51/5271 , H01L51/529 , H01L51/56 , H01L2227/323 , H01L2251/5315
Abstract: A FET is formed on a semiconductor substrate, a curved surface having a radius of curvature is formed on an upper end of an insulation, a portion of a first electrode is exposed corresponding to the curved surface to form an inclined surface, and a region defining a luminescent region is subjected to etching to expose the first electrode. Luminescence emitted from an organic chemical compound layer is reflected by the inclined surface of the first electrode to increase a total quantity of luminescence taken out in a certain direction.
-
公开(公告)号：US09786689B2
公开(公告)日：2017-10-10
申请号：US15063664
申请日：2016-03-08
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Shunpei Yamazaki , Hiroki Ohara , Toshinari Sasaki , Kosei Noda , Hideaki Kuwabara
IPC: H01L29/00 , H01L27/00 , H01L27/12 , G02F1/1337 , G02F1/1368 , G02F1/1333 , G02F1/1343 , G02F1/1362 , H01L29/24 , H01L29/51 , H01L29/786
CPC classification number: H01L27/1225 , G02F1/133345 , G02F1/1337 , G02F1/134309 , G02F1/136227 , G02F1/136277 , G02F1/1368 , H01L27/1214 , H01L27/124 , H01L27/1248 , H01L29/24 , H01L29/517 , H01L29/78609 , H01L29/7869
Abstract: An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.
-
Patent Agency Ranking
公开(公告)号：US09698368B2
公开(公告)日：2017-07-04
申请号：US15172765
申请日：2016-06-03
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Shunpei Yamazaki , Satoshi Seo , Hideaki Kuwabara
Abstract: A FET is formed on a semiconductor substrate, a curved surface having a radius of curvature is formed on an upper end of an insulation, a portion of a first electrode is exposed corresponding to the curved surface to form an inclined surface, and a region defining a luminescent region is subjected to etching to expose the first electrode. Luminescence emitted from an organic chemical compound layer is reflected by the inclined surface of the first electrode to increase a total quantity of luminescence taken out in a certain direction.
-
公开(公告)号：US20170110692A1
公开(公告)日：2017-04-20
申请号：US15392446
申请日：2016-12-28
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Hideaki Kuwabara , Hideto Ohnuma
CPC classification number: H01L51/56 , H01L27/3241 , H01L27/3246 , H01L27/3258 , H01L27/3262 , H01L33/36 , H01L51/0011 , H01L51/52 , H01L2251/5338
Abstract: As a result of miniaturization of a pixel region associated with an improvement in definition and an increase in a substrate size associated with an increase in area, defects due to precision, bending, and the like of a mask used at the time of evaporation have become issues. A partition including portions with different thicknesses over a pixel electrode (also referred to as a first electrode) in a display region and in the vicinity of a pixel electrode layer is formed, without increasing the number of steps, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function made of a diffraction grating pattern or a semi-transmissive film.
-
公开(公告)号：US20160218160A1
公开(公告)日：2016-07-28
申请号：US15091643
申请日：2016-04-06
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Shunpei Yamazaki , Masaaki Hiroki , Masakazu Murakami , Hideaki Kuwabara
CPC classification number: H01L27/3248 , H01L27/3211 , H01L27/3216 , H01L27/322 , H01L27/3246 , H01L27/3272 , H01L27/3276 , H01L27/3279 , H01L51/5212 , H01L51/5228 , H01L51/5253 , H01L2251/5315 , Y10S257/929
Abstract: To provide a light emitting device high in reliability with a pixel portion having high definition with a large screen. According to a light emitting device of the present invention, on an insulator (24) provided between pixel electrodes, an auxiliary electrode (21) made of a metal film is formed, whereby a conductive layer (20) made of a transparent conductive film in contact with the auxiliary electrode can be made low in resistance and thin. Also, the auxiliary electrode (21) is used to achieve connection with an electrode on a lower layer, whereby the electrode can be led out with the transparent conductive film formed on an EL layer. Further, a protective film (32) made of a film containing hydrogen and a silicon nitride film which are laminated is formed, whereby high reliability can be achieved.
-
公开(公告)号：USD753108S1
公开(公告)日：2016-04-05
申请号：US29486859
申请日：2014-04-03
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Designer： Hideaki Kuwabara , Masaaki Hiroki
-
公开(公告)号：US09059216B2
公开(公告)日：2015-06-16
申请号：US13792381
申请日：2013-03-11
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Shunpei Yamazaki , Jun Koyama , Hideaki Kuwabara , Saishi Fujikawa
IPC: H01L31/062 , H01L29/66 , G02F1/1345 , H01L27/15 , H01L27/12
CPC classification number: H01L27/1222 , G02F1/13454 , G02F1/13458 , H01L27/124 , H01L27/156 , H01L29/6675 , H01L29/66765
Abstract: In a display device such as a liquid crystal display device, a large-sized display screen is realized under low power consumption. A surface of a source wiring line of a pixel portion employed in an active matrix type liquid crystal display device is processed by way of a plating process operation so as to lower a resistance value of this source wiring line. The source wiring line of the pixel portion is manufactured at a step different from a step for manufacturing a source wiring line of a drive circuit portion. Further, electrodes of a terminal portion are processed by a plating process operation so as to reduce a resistance value thereof.
-
-
-
-
-
-
-
-
-
Search Results
184
records
(took 0.044 seconds)
