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公开(公告)号：US20150009438A1
公开(公告)日：2015-01-08
申请号：US14113582
申请日：2013-07-31
Inventor： Peng Du , Ming hung Shih , Jiali Jiang
IPC: H05K1/02 , G02F1/1362
CPC classification number: H05K1/025 , G02F1/1345 , H05K1/0248 , H05K1/162 , H05K2201/0326 , H05K2201/0391 , H05K2201/09227 , H05K2201/09763 , H05K2201/10136
Abstract: A fanout line structure of an array substrate includes first fanout lines arranged on a fanout area of the array substrate, and second fanout lines arranged on the fanout area of the array substrate. A second conducting film is arranged at a bottom of the second fanout line, a second capacitor is formed between the second conducting film and a first conducting film of the second fanout line, the second capacitor is used to reduce an impedance difference between the fanout lines. Capacitance value of the second capacitor is dependent on an overlapping area between the second conducting film and the first conducting film.
Abstract translation: 阵列基板的扇出线结构包括布置在阵列基板的扇出区域上的第一扇出线和布置在阵列基板的扇出区域上的第二扇出线。 第二导电膜布置在第二扇出线的底部，第二电容器形成在第二导电膜和第二扇出线的第一导电膜之间，第二电容用于降低扇出线之间的阻抗差 。 第二电容器的电容值取决于第二导电膜和第一导电膜之间的重叠面积。
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公开(公告)号：US20190243184A1
公开(公告)日：2019-08-08
申请号：US15328925
申请日：2017-01-06
Inventor： Jianjian Ying , Peng Du
IPC: G02F1/1335 , G02F1/1339
CPC classification number: G02F1/133514 , G02F1/133512 , G02F1/1339
Abstract: Disclosed is a liquid crystal panel. The liquid crystal panel comprises a color filter substrate. The color filter substrate comprises a first glass layer, on which a protective layer is provided. An edge of an active area of the color filter substrate is provided thereon with a black matrix layer and a sealant layer. The black matrix layer is located between the first glass layer and the protective layer. A length of the black matrix layer is smaller than that of the first glass layer. A retaining wall is provided on an upper surface of the black matrix layer, and a sealant layer is arranged at an end of the protective layer. The liquid crystal panel can effectively prevent an overlap between a PI liquid and the sealant, thereby preventing sealant peeling and improving the qualified rate of products.
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公开(公告)号：US10297216B2
公开(公告)日：2019-05-21
申请号：US14907930
申请日：2016-01-12
Inventor： Xiaoxiao Wang , Peng Du
IPC: G09G3/20 , G09G3/36 , G02F1/13 , G02F1/1345 , G02F1/1362
Abstract: A gate driving circuit and an array substrate using the same are described. The gate driving circuit pulls up and pulls down the voltage level of the node in one display frame by a first voltage signal of a second driving module and a second voltage signal of a third driving module to control the high level and low level respectively of scan signal in the scan output terminal for sequentially writing data signal to all the first row sub-pixels, all the second row sub-pixels and all the third row sub-pixels of the one display frame in order to prevent the sub-pixels from RC delay and color deviation, thereby improving the display quality of the LCD.
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公开(公告)号：US10290275B2
公开(公告)日：2019-05-14
申请号：US15327551
申请日：2017-01-13
Inventor： Peng Du
IPC: G09G3/36
Abstract: The present disclosure proposes a driving circuit. The driving circuit includes a gate-driver on array (GOA) unit at n stages and n scan lines. A scan line is arranged on the GOA unit at every stage. GOA units at any two neighboring stages arranged at both sides of the scan line. The GOA unit near the first clock signal line is connected to the first clock signal line. The GOA unit near the second clock signal line is connected to the second clock signal line. The nth stage GOA unit couples to an (n−1)th stage GOA unit and an (n+1)th stage GOA unit.
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公开(公告)号：US10175539B2
公开(公告)日：2019-01-08
申请号：US15123665
申请日：2016-07-11
Inventor： Jianjian Ying , Peng Du , Wen Dai
IPC: G02F1/1337
Abstract: The present application discloses a method of performing photo alignment to a liquid crystal panel and a mask, the method including: disposing a mask in one side of a liquid crystal panel, the mask including at least two regions, the two regions makes incident lights passed and generating emission lights with different polarization directions respectively; making the incident light passed through the mask, to generate the emission lights with different polarization direction, and perform a photo alignment to the different regions of the liquid crystal panel. By the approach above, the process of the photo alignment is changed in the present application, thereby reducing the time of the photo alignment process and increase productivity.
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Patent Agency Ranking
公开(公告)号：US10162236B2
公开(公告)日：2018-12-25
申请号：US14907915
申请日：2015-12-08
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
IPC: H01L29/04 , G02F1/1362 , G02F1/1343 , G02F1/1368 , G02F1/1333 , H01L27/12
Abstract: An array substrate and a liquid crystal display device comprising the array substrate are disclosed. The array substrate comprises a pixel unit having a thin film transistor region and a through-hole region. The pixel unit comprises a glass substrate, a first insulation layer, a second insulation layer, a third insulation layer, a fourth insulation layer, and a fifth insulation layer stacked from bottom up in sequence. In the thin film transistor region, the glass substrate is provided with a light-shading metal member that is covered by the first insulation layer, the first insulation layer is provided with an active layer that is covered by the second insulation layer, two ends of the active layer are respectively connected with a source and a drain formed between the third insulation layer and the fourth insulation layer, the second insulation layer is provided with a gate that is covered by the third insulation layer, and the fourth insulation layer is provided with a common electrode that is covered by the fifth insulation layer. In the through-hole region, a pixel electrode is arranged on the fifth insulation layer and a through hole is configured in the fourth insulation layer, so that the pixel electrode is connected with the source or the drain after passing through the fifth insulation layer. A cushion layer is arranged under the through hole in an insulated manner.
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公开(公告)号：US20180157071A1
公开(公告)日：2018-06-07
申请号：US14907886
申请日：2015-12-07
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
IPC: G02F1/1339 , G02F1/1362 , G02F1/1335 , G02F1/1333
CPC classification number: G02F1/1339 , G02F1/133345 , G02F1/133512 , G02F1/133514 , G02F1/13394 , G02F1/136286
Abstract: Disclosed is a liquid crystal display panel. An array substrate of the liquid crystal display panel comprises at least two pixel units. One pixel unit comprises: a scan line extending along a first direction; a data line extending along a second direction, different from the first direction; a pixel electrode; and a thin film transistor which is disposed in a functional connection between the data line and the pixel electrode. At least a part of the two adjacent pixel units are arranged mirror-symmetrically to each other. A new wire design is provided, so that a spacer can be arranged to avoid a PLN via hole, which effectively prevents the spacer of the panel from sliding into the PLN via hole while a liquid crystal cell is assembled or during a bending test procedure.
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公开(公告)号：US09958743B2
公开(公告)日：2018-05-01
申请号：US14891744
申请日：2015-08-20
Inventor： Peng Du
IPC: G02F1/1345 , G02F1/1362 , G02F1/1368 , G02F1/1343
CPC classification number: G02F1/13454 , G02F1/134309 , G02F1/13624 , G02F1/136286 , G02F1/1368 , G02F2001/134345 , G02F2201/121 , G02F2201/40
Abstract: The present invention provides a liquid crystal display panel, comprising: a control terminal of the first main thin film transistor on the nth row of the pixels connected to a branch of the scanning lines to which the nth row of the pixels correspond; the control terminal of the second main thin film transistor on the nth row of the pixels connected to a first branch of the scanning line of the (n+1)th row; the control terminal of the auxiliary thin film transistor on the (n+1)th row of pixels connected to a branch of the scanning lines of the (n+1)th row.
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公开(公告)号：US09905590B2
公开(公告)日：2018-02-27
申请号：US14779089
申请日：2015-07-31
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor： Cong Wang , Peng Du , Xiaoxiao Wang
IPC: H01L27/12 , H01L29/786 , G02F1/1368
CPC classification number: H01L27/127 , G02F1/1368 , G02F2202/104 , H01L27/1222 , H01L27/1248 , H01L27/1288 , H01L29/78621 , H01L29/78675
Abstract: The present invention provides a LTPS array substrate and a manufacturing method thereof. The method comprises: forming a source electrode and a drain electrode on a substrate, forming polysilicon layers of a first region and a second region on the substrate including the source electrode and the drain electrode, and the thickness of the polysilicon layer of the first region is greater than the one of the second region, the polysilicon layer of the first region partially covers the source electrode and the drain electrode; passivating the surface of the polysilicon layer in order to turn the part of the adjacent surface of the polysilicon layer of the second region and the first region into an insulating layer; forming a gate electrode on the insulating layer between the source electrode and the drain electrode. The present invention can simplify the LTPS technical process and reduce the producing costs.
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公开(公告)号：US09899425B2
公开(公告)日：2018-02-20
申请号：US14781536
申请日：2015-08-14
IPC: H01L27/14 , H01L27/12 , H01L29/66 , H01L29/49 , H01L29/786 , H01L21/225 , H01L21/265
CPC classification number: H01L27/124 , H01L21/2253 , H01L21/26513 , H01L29/4908 , H01L29/66757 , H01L29/78618 , H01L29/78675
Abstract: A manufacturing method for an array substrate is provided in the present invention. The method comprises: forming a Poly-Silicon layer on a glass substrate; forming heavily doped regions by performing heavily doping and activation process at both sides of the Poly-Silicon layer; forming a source/a drain of a first metal layer growing on the heavily doped region; forming a gate of both a gate insulator and a second metal layer growing sequentially on the Poly-Silicon layer, wherein, a material of the second metal layer is aluminum. The activation technology process can be improved in the present invention to reduce RC delay in metal wires of product and then further to achieve large sizes for products.
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