公开(公告)号：US10964551B2

公开(公告)日：2021-03-30

申请号：US15085678

申请日：2016-03-30

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L21/67 ,  H01L21/677 ,  H01L21/321 ,  B24B37/005 ,  H01L21/02 ,  H01L21/66

Abstract: CMP selectivity, removal rate, and uniformity are controlled both locally and globally by altering electric charge at the wafer surface. Surface charge characterization is performed by an on-board metrology module. Based on a charge profile map, the wafer can be treated in an immersion bath to impart a more positive or negative charge overall, or to neutralize the entire wafer before the CMP operation is performed. If charge hot spots are detected on the wafer, a charge pencil can be used to neutralize localized areas. One type of charge pencil bears a tapered porous polymer tip that is placed in close proximity to the wafer surface. Films present on the wafer absorb ions from, or surrender ions to, the charge pencil tip, by electrostatic forces. The charge pencil can be incorporated into a CMP system to provide an in-situ treatment prior to the planarization step or the slurry removal step.

公开(公告)号：US10950722B2

公开(公告)日：2021-03-16

申请号：US14588337

申请日：2014-12-31

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John H. Zhang ,  Carl Radens ,  Lawrence A. Clevenger ,  Yiheng Xu

IPC: H01L29/78 ,  H01L29/165 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238

Abstract: Vertical GAA FET structures are disclosed in which a current-carrying nanowire is oriented substantially perpendicular to the surface of a silicon substrate. The vertical GAA FET is intended to meet design and performance criteria for the 7 nm technology generation. In some embodiments, electrical contacts to the drain and gate terminals of the vertically oriented GAA FET can be made via the backside of the substrate. Examples are disclosed in which various n-type and p-type transistor designs have different contact configurations. In one example, a backside gate contact extends through the isolation region between adjacent devices. Other embodiments feature dual gate contacts for circuit design flexibility. The different contact configurations can be used to adjust metal pattern density.

公开(公告)号：US10910385B2

公开(公告)日：2021-02-02

申请号：US16510612

申请日：2019-07-12

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. Zhang

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78 ,  H01L29/20 ,  H01L29/66 ,  H01L21/28 ,  H01L29/10 ,  B82Y10/00 ,  H01L29/775 ,  H01L27/08 ,  H01L27/092 ,  H01L29/739 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/786 ,  H01L31/0392 ,  H01L33/04 ,  H01L45/00 ,  H01L29/49

Abstract: A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes.

公开(公告)号：US10573756B2

公开(公告)日：2020-02-25

申请号：US16228620

申请日：2018-12-20

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. Zhang

IPC: H01L29/786 ,  H01L29/775 ,  H01L29/66 ,  H01L29/40 ,  H01L29/417 ,  H01L29/778 ,  H01L29/41 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/12 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/165

Abstract: Metal quantum dots are incorporated into doped source and drain regions of a MOSFET array to assist in controlling transistor performance by altering the energy gap of the semiconductor crystal. In a first example, the quantum dots are incorporated into ion-doped source and drain regions. In a second example, the quantum dots are incorporated into epitaxially doped source and drain regions.

公开(公告)号：US10438856B2

公开(公告)日：2019-10-08

申请号：US13856325

申请日：2013-04-03

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang ,  Chengyu Niu ,  Heng Yang

IPC: H01L21/70 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/49 ,  H01L21/28 ,  H01L29/78 ,  H01L21/285 ,  H01L29/417 ,  H01L29/66 ,  H01L27/092

Abstract: Methods and devices for enhancing mobility of charge carriers. An integrated circuit may include semiconductor devices of two types. The first type of device may include a metallic gate and a channel strained in a first manner. The second type of device may include a metallic gate and a channel strained in a second manner. The gates may include, collectively, three or fewer metallic materials. The gates may share a same metallic material. A method of forming the semiconductor devices on an integrated circuit may include depositing first and second metallic layers in first and second regions of the integrated circuit corresponding to the first and second gates, respectively.

公开(公告)号：US20190259673A1

公开(公告)日：2019-08-22

申请号：US16399808

申请日：2019-04-30

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L21/84 ,  H01L29/66 ,  H01L29/161 ,  H01L29/423 ,  H01L29/06 ,  H01L29/10 ,  H01L21/266 ,  H01L27/12 ,  H01L27/02 ,  H01L21/308 ,  H01L21/265

Abstract: An analog integrated circuit is disclosed in which short channel transistors are stacked on top of long channel transistors, vertically separated by an insulating layer. With such a design, it is possible to produce a high density, high power, and high performance analog integrated circuit chip including both short and long channel devices that are spaced far enough apart from one another to avoid crosstalk. In one embodiment, the transistors are FinFETs and the long channel devices are multi-gate FinFETs. In one embodiment, single and dual damascene devices are combined in a multi-layer integrated circuit cell. The cell may contain various combinations and configurations of the short and long-channel devices. A high density cell can be made by simply shrinking the dimensions of the cells and replicating two or more cells in the same size footprint as the original cell.

公开(公告)号：US10388659B2

公开(公告)日：2019-08-20

申请号：US15939108

申请日：2018-03-28

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L21/00 ,  H01L21/8238 ,  H01L27/108 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78 ,  H01L29/20 ,  H01L29/66 ,  H01L21/28 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786 ,  H01L29/10 ,  B82Y10/00 ,  H01L29/775 ,  H01L27/08 ,  H01L31/0392 ,  H01L33/04 ,  H01L45/00 ,  H01L29/739 ,  H01L29/49

Abstract: A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes.

公开(公告)号：US10388639B2

公开(公告)日：2019-08-20

申请号：US15802525

申请日：2017-11-03

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Lawrence A. Clevenger ,  Carl J. Radens ,  Yiheng Xu ,  John H. Zhang

IPC: H01L21/44 ,  H01L21/48 ,  H01L25/18 ,  H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L23/13 ,  H01L23/15 ,  H01L23/538

Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the first stair, wherein the at least one additional chip is vertically spaced apart from the first chip.

公开(公告)号：US20190196101A1

公开(公告)日：2019-06-27

申请号：US16292047

申请日：2019-03-04

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: G02B6/132 ,  G02B6/136 ,  H01L23/522 ,  G02B6/122 ,  H01L21/768 ,  G02B6/13 ,  H01L21/66

CPC classification number: G02B6/132 ,  G02B6/122 ,  G02B6/1225 ,  G02B6/13 ,  G02B6/136 ,  G02B2006/121 ,  H01L21/76802 ,  H01L21/76879 ,  H01L21/76883 ,  H01L22/12 ,  H01L22/14 ,  H01L23/522 ,  H01L23/53209 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A sequence of processing steps presented herein is used to embed an optical signal path within an array of nanowires, using only one lithography step. Using the techniques disclosed, it is not necessary to mask electrical features while forming optical features, and vice versa. Instead, optical and electrical signal paths can be created substantially simultaneously in the same masking cycle. This is made possible by a disparity in the widths of the respective features, the optical signal paths being significantly wider than the electrical ones. Using a damascene process, the structures of disparate widths are plated with metal that over-fills narrow trenches and under-fills a wide trench. An optical cladding material can then be deposited into the trench so as to surround an optical core for light transmission.

公开(公告)号：US10319647B2

公开(公告)日：2019-06-11

申请号：US15890001

申请日：2018-02-06

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L27/12 ,  H01L21/84 ,  H01L27/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L21/265 ,  H01L21/266 ,  H01L21/308 ,  H01L29/161 ,  H01L29/423

Abstract: An analog integrated circuit is disclosed in which short channel transistors are stacked on top of long channel transistors, vertically separated by an insulating layer. With such a design, it is possible to produce a high density, high power, and high performance analog integrated circuit chip including both short and long channel devices that are spaced far enough apart from one another to avoid crosstalk. In one embodiment, the transistors are FinFETs and the long channel devices are multi-gate FinFETs. In one embodiment, single and dual damascene devices are combined in a multi-layer integrated circuit cell. The cell may contain various combinations and configurations of the short and long-channel devices. A high density cell can be made by simply shrinking the dimensions of the cells and replicating two or more cells in the same size footprint as the original cell.