公开(公告)号：US09127994B2

公开(公告)日：2015-09-08

申请号：US13953571

申请日：2013-07-29

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero

IPC: G01L1/00 ,  H01L29/66 ,  G01L1/14 ,  G01L11/00 ,  G01L1/22 ,  H01L27/06 ,  G01L25/00

CPC classification number: G01R31/2872 ,  G01L1/00 ,  G01L1/005 ,  G01L1/148 ,  G01L1/225 ,  G01L1/2293 ,  G01L11/00 ,  G01L25/00 ,  G01R31/2884 ,  H01L27/06 ,  H01L29/66007

Abstract: A method for manufacturing an integrated circuit includes forming in a substrate a measuring circuit sensitive to mechanical stresses and configured to supply a measurement signal representative of mechanical stresses exerted on the measuring circuit. The measuring circuit is positioned such that the measurement signal is also representative of mechanical stresses exerted on a functional circuit of the integrated circuit. A method of using the integrated circuit includes determining from the measurement signal the value of a parameter of the functional circuit predicted to mitigate an impact of the variation in mechanical stresses on the operation of the functional circuit, and supplying the functional circuit with the determined value of the parameter.

Abstract translation: 一种用于制造集成电路的方法包括在基板上形成对机械应力敏感的测量电路，并且被配置为提供表示施加在测量电路上的机械应力的测量信号。 测量电路被定位成使得测量信号也代表施加在集成电路的功能电路上的机械应力。 使用集成电路的方法包括从测量信号确定预测的功能电路的参数的值，以减轻机械应力的变化对功能电路的操作的影响，以及向功能电路提供确定的值 的参数。

公开(公告)号：US20150249132A1

公开(公告)日：2015-09-03

申请号：US14627281

申请日：2015-02-20

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Guilhem Bouton ,  Pascal Fornara

IPC: H01L29/10 ,  H01L21/762 ,  H01L21/763 ,  H01L29/06

CPC classification number: H01L29/1083 ,  H01L21/76224 ,  H01L21/763 ,  H01L27/11293 ,  H01L29/0649 ,  H01L29/78 ,  H01L29/7846

Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.

Abstract translation: 集成电路包括衬底和至少一个对压缩应力非常敏感的部件，其至少部分地布置在由绝缘区域限制的衬底的有源区域内。 为了解决有源区域中的压缩应力，电路还包括位于至少绝缘区域中的至少一个电惰性沟槽，并且包含被配置为减小有源区域中的压缩应力的内部区域。 内部填充多晶硅。 多晶硅填充沟槽可以进一步延伸穿过绝缘区域并进入衬底。

公开(公告)号：US20130147004A1

公开(公告)日：2013-06-13

申请号：US13688022

申请日：2012-11-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Antonio di-Giacomo

IPC: H01L49/02

CPC classification number: H01L28/40 ,  G01K5/486 ,  G01K5/62

Abstract: An integrated circuit, comprising a capacitive device having a thermally variable capacitive value and comprising a thermally deformable assembly disposed within an enclosure, and comprising an electrically-conducting fixed body and a beam held at at least two different locations by at least two arms rigidly attached to edges of the enclosure, the beam and the arms being metal and disposed within the first metallization level. A part of the said thermally deformable assembly may form a first electrode of the capacitive device and a part of the said fixed body may form a second electrode of the capacitive device. The thermally deformable assembly has a plurality of configurations corresponding respectively to various temperatures of the said assembly and resulting in a plurality of distances separating the two electrodes and various capacitive values in the capacitive device corresponding to the plurality of distances.

Abstract translation: 一种集成电路，包括具有热可变电容值的电容性装置，并且包括设置在外壳内的可热变形组件，并且包括导电固定体和通过至少两个不同位置固定的梁，刚性连接 到外壳的边缘，梁和臂是金属的并且设置在第一金属化水平内。 所述热变形组件的一部分可以形成电容性装置的第一电极，并且所述固定体的一部分可以形成电容性装置的第二电极。 热变形组件具有分别对应于所述组件的各种温度的多个构造，并且导致分离两个电极的多个距离和对应于多个距离的电容式装置中的各种电容值。

公开(公告)号：US20130104950A1

公开(公告)日：2013-05-02

申请号：US13659622

申请日：2012-10-24

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero

IPC: H01L35/02

CPC classification number: H01L27/16 ,  H01L23/38 ,  H01L35/02 ,  H01L35/34 ,  H01L2224/16225 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Method of wireless communication between a first device and a second device, in which, the first device and the second device comprising respectively a first thermoelectric generator and a second thermoelectric generator, the two thermoelectric generators being in thermal coupling, a first signal is generated within the first device, the first thermoelectric generator is electrically powered as a function of the first signal so as to create a first thermal gradient in the said first generator and a second thermal gradient in the second generator, and a second signal is generated within the second device on the basis of the electrical energy produced by the second thermoelectric generator in response to the said second thermal gradient.

Abstract translation: 第一装置和第二装置之间的无线通信方法，其中第一装置和第二装置分别包括第一热电发电机和第二热电发电机，两个热电发生器处于热耦合中，第一信号在内部产生 所述第一装置，所述第一热电发电机作为所述第一信号的功能而被供电，以在所述第一发生器中产生第一热梯度，并且在所述第二发生器中产生第二热梯度，并且在所述第二发生器内产生第二信号 基于由第二热电发电机响应于所述第二热梯度产生的电能的装置。

公开(公告)号：US11581270B2

公开(公告)日：2023-02-14

申请号：US17014058

申请日：2020-09-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien Delalleau ,  Christian Rivero

IPC: H01L23/52 ,  H01L23/00 ,  H01L23/528 ,  H01L29/06 ,  H01L27/088 ,  H01L29/10 ,  H01L27/02 ,  H01L29/08 ,  H01L21/8234 ,  H01L21/3205 ,  H01L21/3213 ,  H01L29/49 ,  H01L29/45

Abstract: An integrated circuit includes a substrate, an interconnection part, and an isolating region located between the substrate and the interconnection part. A decoy structure is located within the isolating region and includes a silicided sector which is electrically isolated from the substrate.

公开(公告)号：US10804222B2

公开(公告)日：2020-10-13

申请号：US16036639

申请日：2018-07-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien Delalleau ,  Christian Rivero

IPC: H01L29/08 ,  H01L23/00 ,  H01L23/528 ,  H01L29/06 ,  H01L27/088 ,  H01L29/10 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/3205 ,  H01L21/3213 ,  H01L29/49 ,  H01L29/45

Abstract: An integrated circuit includes a substrate, an interconnection part, and an isolating region located between the substrate and the interconnection part. A decoy structure is located within the isolating region and includes a silicided sector which is electrically isolated from the substrate.

公开(公告)号：US10796992B2

公开(公告)日：2020-10-06

申请号：US16260394

申请日：2019-01-29

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Jean-Philippe Escales

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L21/311 ,  H01L23/31

Abstract: A stack including a dual-passivation is etched locally so as to reveal contact pads of an integrated circuit which are situated above a last metallization level of an interconnection part of the integrated circuit. This stack serves to protect the integrated circuit against a breakdown of at least one dielectric region, at least in part porous, separating two electrically conducting elements of the interconnection part of the integrated circuit. Such a breakdown may occur due to electrical conduction assisted by the presence of defects within the at least one dielectric region.

公开(公告)号：US10770409B2

公开(公告)日：2020-09-08

申请号：US16051680

申请日：2018-08-01

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki ,  Christian Rivero ,  Quentin Hubert

IPC: G06K19/073 ,  G06F21/75 ,  H01L23/00 ,  H01L27/02

Abstract: An integrated electronic circuit includes a semiconductor substrate with a semiconductor well that is isolated by a buried semiconductor region located under the semiconductor well. A vertical MOS transistor formed in the semiconductor well includes a source-drain region provided by the buried semiconductor region. Backside thinning of the semiconductor substrate is detected by biasing the vertical MOS transistor into an on condition to supply a current and then comparing that current to a threshold. Current less than a threshold is indicative that the semiconductor substrate has been thinned from the backside.

公开(公告)号：US10748726B2

公开(公告)日：2020-08-18

申请号：US16222017

申请日：2018-12-17

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Antonio Di-Giacomo ,  Brice Arrazat

IPC: H01H1/58 ,  H01H61/02 ,  H01H9/02 ,  B81B3/00

Abstract: A device includes a thermally deformable assembly accommodated in a cavity of the interconnection part of an integrated circuit. The assembly can bend when there is a variation in temperature, so that its free end zone is displaced vertically. The assembly can be formed in the back end of line of the integrated circuit.

公开(公告)号：US10714583B2

公开(公告)日：2020-07-14

申请号：US16037095

申请日：2018-07-17

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Guilhem Bouton ,  Pascal Fornara ,  Julien Delalleau

IPC: H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L21/28 ,  H01L21/8234

Abstract: A MOS transistor is produced on and in an active zone which includes a source region and a drain region. The active zone is surrounded by an insulating region. A conductive gate region of the transistor has two flanks which extend transversely to a source-drain direction, and the conductive gate region overlaps two opposite edges of the active zone act overlap zones. The conductive gate region includes, at a location of at least one overlap zone, at least one conductive tag which projects from at least one flank at a foot of the conductive gate region. The conductive tag covers a part of the active zone and a part of the insulating region.