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    Method for Writing in an EEPROM Memory and Corresponding Memory
    71.
    发明申请
    Method for Writing in an EEPROM Memory and Corresponding Memory 有权
    写入EEPROM存储器和相应存储器的方法

    公开(公告)号：US20170039001A1

    公开(公告)日：2017-02-09

    申请号：US15055546

    申请日：2016-02-27

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： François Tailliet ,  Marc Battista

    IPC: G06F3/06 ,  G11C29/52 ,  G06F11/10

    CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0652 ,  G06F3/0679 ,  G06F11/1068 ,  G11C16/10 ,  G11C16/3495 ,  G11C29/52

    Abstract: According to one mode of implementation it is proposed to automatically accelerate the write operation by deleting on the basis of the values of the data to be written and optionally on the basis of the values of the data present in the memory the erasure step or the programming step, so doing while optionally using a conventional write command. When the memory is equipped with an error-correcting code based on a Hamming code, a property of the latter makes it possible readily to implement this possible acceleration of the cycles of writings within the memory. This property is that according to which when all the bits of the bytes of a digital word grouping together n bytes are equal to zero, the check bits associated with these bytes are also all equal to zero.

    Abstract translation: 根据一种实现方式，提出通过基于要写入的数据的值进行删除来自动加速写入操作，并且可选地基于存储在存储器中的数据的值擦除步骤或编程 这样做，同时可选地使用常规写入命令。 当存储器配备有基于汉明码的纠错码时，后者的特性使得可能容易地实现该存储器内写入循环的这种可能的加速。 该属性是根据该属性，当将n个字节组合在一起的数字字的所有位都等于零时，与这些字节相关联的校验位也全部等于零。

    Semiconductor Structure and Memory Device including the Structure
    73.
    发明申请
    Semiconductor Structure and Memory Device including the Structure 有权
    包括结构的半导体结构和存储器件

    公开(公告)号：US20150269989A1

    公开(公告)日：2015-09-24

    申请号：US14657914

    申请日：2015-03-13

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： François Tailliet ,  Marc Battista

    IPC: G11C11/41 ,  H01L27/11 ,  G11C14/00 ,  G11C16/04

    CPC classification number: G11C11/41 ,  G11C11/4125 ,  G11C14/0054 ,  G11C14/0063 ,  G11C16/0416 ,  H01L23/5226 ,  H01L27/1104 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/518 ,  H01L29/788

    Abstract: A semiconductor structure includes first and second source/drain region disposed in a semiconductor body and spaced from each other by a channel region. A gate electrode overlies the channel region and a capacitor electrode is disposed between the gate electrode and the channel region. A first gate dielectric is disposed between the gate electrode and the capacitor electrode and a second gate dielectric disposed between the capacitor electrode and the channel region. A first electrically conductive contact region is in electrical contact with the gate electrode and a second electrically conductive contact region in electrical contact with the capacitor electrode. The first and second contact regions are electrically isolated from one another.

    Abstract translation: 半导体结构包括设置在半导体本体中并通过沟道区彼此隔开的第一和第二源/漏区。 栅电极覆盖沟道区域，电容器电极设置在栅电极和沟道区之间。 第一栅极电介质设置在栅电极和电容器电极之间，第二栅极电介质设置在电容器电极和沟道区之间。 第一导电接触区域与栅电极电接触，以及与电容器电极电接触的第二导电接触区域。 第一和第二接触区域彼此电隔离。

    Method for managing the operation of a memory device having a SRAM memory plane and a non volatile memory plane, and corresponding memory device
    74.
    发明授权
    Method for managing the operation of a memory device having a SRAM memory plane and a non volatile memory plane, and corresponding memory device 有权
    用于管理具有SRAM存储器平面和非易失性存储器平面的存储器件的操作的方法以及相应的存储器件

    公开(公告)号：US09123413B2

    公开(公告)日：2015-09-01

    申请号：US14315401

    申请日：2014-06-26

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： François Tailliet ,  Marc Battista

    IPC: G11C11/34 ,  G11C14/00 ,  G11C7/10 ,  G11C16/04 ,  G11C16/34

    CPC classification number: G11C14/0063 ,  G11C7/1006 ,  G11C16/0408 ,  G11C16/3418

    Abstract: A method can be used for managing the operation of a memory cell that includes an SRAM elementary memory cell and a non-volatile elementary memory cell coupled to one another. A data bit is transferred between the SRAM elementary memory cell and the non-volatile elementary memory cell. A control datum is stored in a control memory cell that is functionally analogous to and associated with the memory cell. The data bit is read from the SRAM elementary memory cell and a corresponding read of the control datum is performed. The data bit read from the SRAM elementary memory cell is inverted if the control datum has a first value but the data bit read from the SRAM elementary memory cell is not inverted if the control datum has a second value.

    Abstract translation: 一种方法可用于管理包括彼此耦合的SRAM基本存储单元和非易失性基本存储单元的存储单元的操作。 数据位在SRAM单元存储单元和非易失性单元存储单元之间传送。 控制数据被存储在功能上类似于存储器单元并与其相关联的控制存储器单元中。 从SRAM基本存储单元读取数据位，并执行相应的控制数据读取。 如果控制数据具有第一值，则从SRAM基本存储器单元读取的数据位被反转，但是如果控制数据具有第二值，则从SRAM基本存储单元读取的数据位不反转。

    Method for addressing a non-volatile memory on I2C bus and corresponding memory device
    76.
    发明授权
    Method for addressing a non-volatile memory on I2C bus and corresponding memory device 有权

    公开(公告)号：US11127468B2

    公开(公告)日：2021-09-21

    申请号：US15842586

    申请日：2017-12-14

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： François Tailliet ,  Marc Battista

    IPC: G06F12/02 ,  G11C16/20 ,  G11C16/10 ,  G11C11/56 ,  G11C16/12 ,  G06F13/42 ,  G06F9/30

    Abstract: Some embodiments include a method for addressing an integrated circuit for a non-volatile memory of the EEPROM type on a bus of the I2C type. The memory includes J hardware-identification pins, with J being an integer lying between 1 and 3, which are assigned respective potentials defining an assignment code on J bits. The method includes a first mode of addressing used selectively when the assignment code is equal to a fixed reference code on J bits, and a second mode of addressing used selectively when the assignment code is different from the reference code. In the first mode, the memory plane of the non-volatile memory is addressed by a memory address contained in the last low-order bits of the slave address and in the first N bytes received. In the second mode, the memory plane is addressed by a memory address contained in the first N+1 bytes received.

    MOS transistors in parallel
    78.
    发明授权
    MOS transistors in parallel 有权

    公开(公告)号：US10892321B2

    公开(公告)日：2021-01-12

    申请号：US16059654

    申请日：2018-08-09

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： François Tailliet

    IPC: H01L29/76 ,  H01L29/06 ,  H01L27/088 ,  H01L21/762 ,  H01L29/10 ,  H01L29/78 ,  H01L21/8234

    Abstract: An electronic chip includes first transistors connected in parallel so that gates of the first transistors are interconnected, drain areas of the first transistors are interconnected, and source areas of the first transistors are interconnected. The first transistors are separated from one another by first isolating trenches. The chip also includes second transistors and second isolating trenches. The second transistors are separated from one another by the second isolating trenches. The first isolating trenches have a maximum width that is smaller than a maximum width of all the second isolating trenches.

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