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    Method Of Forming A Device With FINFET Split Gate Non-volatile Memory Cells And FINFET Logic Devices
    73.
    发明申请
    Method Of Forming A Device With FINFET Split Gate Non-volatile Memory Cells And FINFET Logic Devices 有权

    公开(公告)号：US20210272973A1

    公开(公告)日：2021-09-02

    申请号：US16803876

    申请日：2020-02-27

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Feng Zhou ,  Xian Liu ,  JinHo Kim ,  Serguei Jourba ,  Catherine Decobert ,  Nhan Do

    IPC: H01L27/11534 ,  H01L27/11521

    Abstract: A method of forming a device with a silicon substrate having upwardly extending first and second fins. A first implantation forms a first source region in the first silicon fin. A second implantation forms a first drain region in the first silicon fin, and second source and drain regions in the second silicon fin. A first channel region extends between the first source and drain regions. A second channel region extends between the second source and drain regions. A first polysilicon deposition is used to form a floating gate that wraps around a first portion of the first channel region. A second polysilicon deposition is used to form an erase gate wrapping around first source region, a word line gate wrapping around a second portion of the first channel region, and a dummy gate wrapping around the second channel region. The dummy gate is replaced with a metal gate.

    Method of forming split gate memory cells
    75.
    发明授权
    Method of forming split gate memory cells 有权

    公开(公告)号：US11081553B2

    公开(公告)日：2021-08-03

    申请号：US16868143

    申请日：2020-05-06

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Leo Xing ,  Chunming Wang ,  Guo Yong Liu ,  Melvin Diao ,  Xian Liu ,  Nhan Do

    IPC: H01L21/00 ,  H01L21/28 ,  H01L27/11521 ,  H01L27/11531 ,  H01L29/423 ,  H01L21/265 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/788

    Abstract: A method of forming a memory device includes forming a second insulation layer on a first conductive layer formed on a first insulation layer formed on semiconductor substrate. A trench is formed into the second insulation layer extending down and exposing a portion of the first conductive layer, which is etched or oxidized to have a concave upper surface. Two insulation spacers are formed along sidewalls of the trench, having inner surfaces facing each other and outer surfaces facing away from each other. A source region is formed in the substrate between the insulation spacers. The second insulation layer and portions of the first conductive layer are removed to form floating gates under the insulation spacers. A third insulation layer is formed on side surfaces of the floating gates. Two conductive spacers are formed along the outer surfaces. Drain regions are formed in the substrate adjacent the conductive spacers.

    Method Of Forming Split-Gate Flash Memory Cell With Spacer Defined Floating Gate And Discretely Formed Polysilicon Gates
    79.
    发明申请
    Method Of Forming Split-Gate Flash Memory Cell With Spacer Defined Floating Gate And Discretely Formed Polysilicon Gates 有权

    公开(公告)号：US20210005724A1

    公开(公告)日：2021-01-07

    申请号：US16796412

    申请日：2020-02-20

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Chunming Wang ,  Xian Liu ,  Nhan Do ,  Leo Xing ,  Guo Yong Liu ,  Melvin Diao

    IPC: H01L21/28 ,  H01L27/11521

    Abstract: A method of forming a memory device that includes forming a first polysilicon layer using a first polysilicon deposition over a semiconductor substrate, forming an insulation spacer on the first polysilicon layer, and removing some of the first polysilicon layer to leave a first polysilicon block under the insulation spacer. A source region is formed in the substrate adjacent a first side surface of the first polysilicon block. A second polysilicon layer is formed using a second polysilicon deposition. The second polysilicon layer is partially removed to leave a second polysilicon block over the substrate and adjacent to a second side surface of the first polysilicon block. A third polysilicon layer is formed using a third polysilicon deposition. The third polysilicon layer is partially removed to leave a third polysilicon block over the source region. A drain region is formed in the substrate adjacent to the second polysilicon block.

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