公开(公告)号：US07986582B2

公开(公告)日：2011-07-26

申请号：US12186195

申请日：2008-08-05

申请人： Hermann Ruckerbauer ,  Christian Sichert

发明人： Hermann Ruckerbauer ,  Christian Sichert

IPC分类号： G11C8/00

CPC分类号： G11C8/12 ,  G11C5/04 ,  G11C8/08 ,  G11C8/14

摘要： A method for operating a memory apparatus which comprises at least two memory devices, each memory device containing at least one bank, comprising: activation of at least one word line in at least one bank on the basis of a row activation command; storage of bank information, the bank information indicating which banks per memory device contain a word line activated by the row activation command; reading/writing of memory contents from/to banks with activated word lines on the basis of the bank information.

摘要翻译： 一种用于操作包括至少两个存储器设备的存储器设备的方法，每个存储器设备包含至少一个存储体，包括：基于行激活命令激活至少一个存储体中的至少一个字线; 存储银行信息，所述银行信息指示每个存储器设备的哪些存储体包含由行激活命令激活的字线; 根据银行信息，从活动字线向银行读/写存储内容。

公开(公告)号：US07957209B2

公开(公告)日：2011-06-07

申请号：US12180814

申请日：2008-07-28

申请人： Hermann Ruckerbauer

发明人： Hermann Ruckerbauer

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C8/12 ,  G11C8/08

摘要： A memory apparatus includes at least two memory devices, each memory device including at least one memory bank. A method of operating the memory apparatus includes receiving a row activation command generated by a memory controller, wherein the row activation command includes a bank address. The method also includes activating a word line in a bank of one of the memory devices based on the row activation command, wherein the bank address is used to select the memory device.

摘要翻译： 存储装置包括至少两个存储器件，每个存储器件包括至少一个存储体。 操作存储装置的方法包括接收由存储器控制器产生的行激活命令，其中行激活命令包括存储体地址。 该方法还包括基于行激活命令来激活存储器设备之一的存储体中的字线，其中存储体地址用于选择存储器件。

公开(公告)号：US07956665B2

公开(公告)日：2011-06-07

申请号：US12040473

申请日：2008-02-29

申请人： Daniel Kehrer ,  Hermann Ruckerbauer ,  Martin Streibl

发明人： Daniel Kehrer ,  Hermann Ruckerbauer ,  Martin Streibl

IPC分类号： H03K3/00

CPC分类号： G06F1/10 ,  H03K23/40

摘要： Embodiments of the invention relate to an integrated circuit comprising at least one functional unit configured to operate at a first clock frequency. The integrated circuit also comprises at least one first interconnect originating from a contact pad and leading to at least one frequency divider configured to receive a clock signal having a second frequency and generate one or more clock signals to operate the functional unit at the first frequency. The integrated circuit further comprises at least one second interconnect coupling an output of the frequency divider and an input of the functional unit, wherein a total length of the second wired interconnect is less than a total length of the first wired interconnects.

摘要翻译： 本发明的实施例涉及一种集成电路，其包括被配置为以第一时钟频率操作的至少一个功能单元。 集成电路还包括源自接触焊盘的至少一个第一互连件，并且通向至少一个分频器，该至少一个分频器配置成接收具有第二频率的时钟信号，并产生一个或多个时钟信号以在第一频率下操作功能单元。 集成电路还包括耦合分频器的输出和功能单元的输入的至少一个第二互连，其中第二有线互连的总长度小于第一有线互连的总长度。

公开(公告)号：US07638869B2

公开(公告)日：2009-12-29

申请号：US11692637

申请日：2007-03-28

申请人： Roland Irsigler ,  Steve Wood ,  Hermann Ruckerbauer ,  Richard Johannes Luyken ,  Carsten Niepelt

发明人： Roland Irsigler ,  Steve Wood ,  Hermann Ruckerbauer ,  Richard Johannes Luyken ,  Carsten Niepelt

IPC分类号： H01L23/48

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05553 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/85 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A semiconductor device having a stacked arrangement of a substrate and a first chip and a second chip is disclosed. In one embodiment, the first chip is arranged with a lower face on an upper face of the substrate; the second chip with a lower face on an upper face of the first chip, whereby a partial area of the upper face of the first chip that is adjacent to an edge of the first chip is uncovered by the second chip; a fifth wire contact pad is arranged on the uncovered area of the upper face of the first chip; a first bonding wire is arranged that is connected with a first wire contact pad of the substrate and the fifth wire contact pad of the first chip.

摘要翻译： 公开了具有基板和第一芯片和第二芯片的堆叠布置的半导体器件。 在一个实施例中，第一芯片布置成在基板的上表面上具有下表面; 所述第二芯片在所述第一芯片的上表面上具有下表面，由此所述第一芯片的与所述第一芯片的边缘相邻的部分区域被所述第二芯片覆盖; 第五线接触垫布置在第一芯片的上表面的未覆盖区域上; 布置第一接合线，其与基板的第一线接触焊盘和第一芯片的第五线接触焊盘连接。

公开(公告)号：US20090268539A1

公开(公告)日：2009-10-29

申请号：US12108383

申请日：2008-04-23

申请人： Hermann Ruckerbauer ,  Dominique Savignac

发明人： Hermann Ruckerbauer ,  Dominique Savignac

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40611 ,  G11C11/40615

摘要： A chip includes a memory array and a refresh counter. The refresh counter is configured to receive refresh trigger signals. The refresh counter is configured or configurable to initiate a refresh of the memory array only once per i of the received refresh trigger signals where i is a number greater than 1.

摘要翻译： 芯片包括存储器阵列和刷新计数器。 刷新计数器被配置为接收刷新触发信号。 刷新计数器被配置或配置为仅在接收到的刷新触发信号（i是大于1的数量）的情况下才开始刷新存储器阵列一次。

公开(公告)号：US07334150B2

公开(公告)日：2008-02-19

申请号：US11002148

申请日：2004-12-03

申请人： Hermann Ruckerbauer ,  Abdallah Bacha ,  Christian Sichert ,  Dominique Savignac ,  Peter Gregorius ,  Paul Wallner

发明人： Hermann Ruckerbauer ,  Abdallah Bacha ,  Christian Sichert ,  Dominique Savignac ,  Peter Gregorius ,  Paul Wallner

IPC分类号： G06F1/04

CPC分类号： G11C5/04 ,  G11C5/063

摘要： A semiconductor memory module includes a plurality of semiconductor memory chips and bus signal lines that supply an incoming clock signal and incoming command and address signals to the semiconductor memory chips. A clock signal regeneration circuit and a register circuit are arranged on the semiconductor memory module in a common chip packing connected to the bus signal lines. The clock signal regeneration circuit and the register circuit respectively condition the incoming clock signal and temporarily store the incoming command and address signals, respectively multiply the conditioned clock signal and the temporarily stored command and address signals by a factor of 1:X, and respectively supply to the semiconductor memory chips the conditioned clock signal and the temporarily stored command and address signals.

摘要翻译： 半导体存储器模块包括多个半导体存储器芯片和总线信号线，其向半导体存储器芯片提供输入时钟信号和输入命令和地址信号。 时钟信号再生电路和寄存器电路以连接到总线信号线的公共芯片封装布置在半导体存储器模块中。 时钟信号再生电路和寄存器电路分别对输入的时钟信号进行调节，并临时存储输入的命令和地址信号，分别将经调节的时钟信号和临时存储的命令和地址信号乘以1：X，分别提供 对半导体存储器芯片调节时钟信号和临时存储的命令和地址信号。

公开(公告)号：US20080022037A1

公开(公告)日：2008-01-24

申请号：US11862915

申请日：2007-09-27

申请人： Hermann Ruckerbauer

发明人： Hermann Ruckerbauer

IPC分类号： G06F12/02

CPC分类号： G11C7/1018 ,  G06F13/1684

摘要： A memory system is functionally designed so that, despite operation without an error correction device, memory chips of a memory module that are actually provided for error correction are concomitantly used for the data transfer. A control device is configured to receive, store and transfer data packets to and from a first and second set of memory chips. Transfer of an internal packet data from the control device to memory takes place such that a first record is stored in a second set of memory chips and additional records are stored in the first set of memory chips. In preferred embodiments, data is allocated in the second set of memory chips such that at least one additional transfer step takes place to the second set of memory chips compared with transfers to the first set of memory chips. In the additional transfer step(s), the first set of memory chips is masked from receiving data.

摘要翻译： 存储器系统在功能上被设计成使得尽管在没有纠错装置的情况下进行操作，但实际提供用于纠错的存储器模块的存储器芯片被同时用于数据传输。 控制装置被配置为接收，存储和传送数据分组到第一和第二组存储器芯片。 将内部分组数据从控制设备传送到存储器进行，使得第一记录被存储在第二组存储器芯片中，并且附加记录被存储在第一组存储器芯片中。 在优选实施例中，在第二组存储器芯片中分配数据，使得与传送到第一组存储器芯片相比，至少一个额外的转移步骤发生到第二组存储器芯片。 在附加传送步骤中，第一组存储器芯片被从接收数据中被掩蔽。

公开(公告)号：US20070228436A1

公开(公告)日：2007-10-04

申请号：US11638310

申请日：2006-12-12

申请人： Hermann Ruckerbauer ,  Holger Schroeter

发明人： Hermann Ruckerbauer ,  Holger Schroeter

IPC分类号： H01L29/94

CPC分类号： H01L25/105 ,  H01L23/5387 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2225/06579 ,  H01L2225/107 ,  H01L2924/15192

摘要： An arrangement of semiconductor memory devices includes a first semiconductor memory device and a second semiconductor memory device. The arrangement of semiconductor memory devices also has a flexible substrate. A first electrically conductive conductor track is arranged in the flexible substrate. At least one first contact of the flexible substrate is coupled to the at least one second contact of the second semiconductor memory device through the first electrically conductive conductor track. A second electrically conductive conductor track is arranged in the flexible substrate.

摘要翻译： 半导体存储器件的布置包括第一半导体存储器件和第二半导体存储器件。 半导体存储器件的布置也具有柔性衬底。 第一导电导体轨道布置在柔性基板中。 柔性基板的至少一个第一接触件通过第一导电导体轨道耦合到第二半导体存储器件的至少一个第二接触件。 第二导电导体轨道布置在柔性基板中。

公开(公告)号：US20070096333A1

公开(公告)日：2007-05-03

申请号：US11263412

申请日：2005-10-31

申请人： Amir Motamedi ,  Hermann Ruckerbauer

发明人： Amir Motamedi ,  Hermann Ruckerbauer

IPC分类号： H01L23/52

CPC分类号： H01L25/0652 ,  H01L23/36 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2224/05599

摘要： A multi-chip package and method is disclosed. In one embodiment, the multi-chip package includes at least four of spaced semiconductor integrated circuit chips mounted on a printed circuit board, consisting of the first pair of the semiconductor integrated circuit chips and the second pair of the semiconductor integrated circuit chips. The chips of the first pair of the semiconductor integrated circuit chips are arranged substantially parallel and the chips of the semiconductor integrated circuit chips of the second pair are arranged substantially stacked over the chips of the first pair of the semiconductor integrated circuit chips.

摘要翻译： 公开了一种多芯片封装和方法。 在一个实施例中，多芯片封装包括安装在由第一对半导体集成电路芯片和第二对半导体集成电路芯片组成的印刷电路板上的间隔开的半导体集成电路芯片中的至少四个。 第一对半导体集成电路芯片的芯片基本上平行布置，并且第二对的半导体集成电路芯片的芯片基本上堆叠在第一对半导体集成电路芯片的芯片上。

公开(公告)号：US20070079057A1

公开(公告)日：2007-04-05

申请号：US11239829

申请日：2005-09-30

申请人： Hermann Ruckerbauer ,  Peter Gregorius

发明人： Hermann Ruckerbauer ,  Peter Gregorius

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F13/1673 ,  G06F13/1684

摘要： A semiconductor memory system is disclosed. In one embodiment, the semiconductor memory system and memory module of the present invention provides a buffer, wherein at least one write buffer chip on the memory module is only buffering and registering write data, command and address signals written from a memory controller to the memory chips. As read data are written back from each memory chip directly to the memory controller through unidirectional point-to-point read data lines the present semiconductor memory system achieves a low latency as compared with a fully buffered DIMM concept. As read data are only unidirectional a high transmission bandwidth can be achieved.

摘要翻译： 公开了半导体存储器系统。 在一个实施例中，本发明的半导体存储器系统和存储器模块提供了缓冲器，其中存储器模块上的至少一个写入缓冲器芯片仅缓冲并将从存储器控制器写入的写数据，命令和地址信号注册到存储器 筹码 由于读取数据通过单向点对点读取数据线直接从每个存储器芯片写回存储器控制器，与全缓冲DIMM概念相比，本半导体存储器系统实现了低延迟。 由于读取数据只是单向的，所以可以实现高传输带宽。