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    Semiconductor device with high K dielectric control terminal spacer structure
    72.
    发明授权
    Semiconductor device with high K dielectric control terminal spacer structure 有权
    具有高K介质控制端子间隔结构的半导体器件

    公开(公告)号：US08349684B2

    公开(公告)日：2013-01-08

    申请号：US12622115

    申请日：2009-11-19

    申请人： Jin Cai ,  Amlan Majumdar ,  Ramachandran Muralidhar ,  Ghavam G. Shahidi

    发明人： Jin Cai ,  Amlan Majumdar ,  Ramachandran Muralidhar ,  Ghavam G. Shahidi

    IPC分类号： H01L21/336

    CPC分类号： H01L29/4983 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

    摘要： A semiconductor device including a control terminal sidewall spacer structure made of a high-K dielectric material. The semiconductor device includes a control terminal where the spacer structure is a sidewall spacer structure for the control terminal. The semiconductor device includes current terminal regions located in a substrate. In some examples, the spacer structure has a height that is less than the height of the control terminal. In some examples, the spacer structure includes portions located over the regions of the substrate between the first current terminal region and the second current terminal region.

    摘要翻译： 一种半导体器件，包括由高K电介质材料制成的控制端子侧壁间隔结构。 半导体器件包括控制端子，其中间隔结构是用于控制端子的侧壁间隔结构。 半导体器件包括位于衬底中的电流端子区域。 在一些示例中，间隔结构的高度小于控制端的高度。 在一些示例中，间隔结构包括位于第一电流端子区域和第二电流端子区域之间的衬底的区域上方的部分。

    MINIMIZING LEAKAGE CURRENT AND JUNCTION CAPACITANCE IN CMOS TRANSISTORS BY UTILIZING DIELECTRIC SPACERS
    73.
    发明申请
    MINIMIZING LEAKAGE CURRENT AND JUNCTION CAPACITANCE IN CMOS TRANSISTORS BY UTILIZING DIELECTRIC SPACERS 失效
    通过使用电介质间隔来最小化CMOS晶体管的漏电流和结电容

    公开(公告)号：US20120261672A1

    公开(公告)日：2012-10-18

    申请号：US13084594

    申请日：2011-04-12

    申请人： Dureseti Chidambarrao ,  Ramachandran Muralidhar ,  Philip J. Oldiges ,  Viorel Ontalus

    发明人： Dureseti Chidambarrao ,  Ramachandran Muralidhar ,  Philip J. Oldiges ,  Viorel Ontalus

    IPC分类号： H01L27/092 ,  H01L21/782 ,  H01L21/8238 ,  H01L27/12

    CPC分类号： H01L21/823814 ,  H01L21/3086 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/84

    摘要： A semiconductor structure and method for forming dielectric spacers and epitaxial layers for a complementary metal-oxide-semiconductor field effect transistor (CMOS transistor) are disclosed. Specifically, the structure and method involves forming dielectric spacers that are disposed in trenches and are adjacent to the silicon substrate, which minimizes leakage current. Furthermore, epitaxial layers are deposited to form source and drain regions, wherein the source region and drain regions are spaced at a distance from each other. The epitaxial layers are disposed adjacent to the dielectric spacers and the transistor body regions (i.e., portion of substrate below the gates), which can minimize transistor junction capacitance. Minimizing transistor junction capacitance can enhance the switching speed of the CMOS transistor. Accordingly, the application of dielectric spacers and epitaxial layers to minimize leakage current and transistor junction capacitance in CMOS transistors can enhance the utility and performance of the CMOS transistors in low power applications.

    摘要翻译： 公开了用于形成用于互补金属氧化物半导体场效应晶体管（CMOS晶体管）的电介质间隔物和外延层的半导体结构和方法。 具体地，该结构和方法包括形成设置在沟槽中并且与硅衬底相邻的电介质间隔物，这使漏电流最小化。 此外，沉积外延层以形成源极和漏极区域，其中源极区域和漏极区域彼此间隔一定距离。 外延层邻近电介质间隔物和晶体管本体区域（即，栅极下方的衬底部分）设置，这可使晶体管结电容最小化。 最小化晶体管结电容可以提高CMOS晶体管的开关速度。 因此，应用介电间隔物和外延层以最小化CMOS晶体管中的漏电流和晶体管结电容可以增强低功率应用中CMOS晶体管的效用和性能。

    Phase change memory cell with heater and method therefor
    74.
    发明授权
    Phase change memory cell with heater and method therefor 有权
    具有加热器的相变存储器单元及其方法

    公开(公告)号：US08043888B2

    公开(公告)日：2011-10-25

    申请号：US12016733

    申请日：2008-01-18

    申请人： Leo Mathew ,  Dharmesh Jawarani ,  Tushar P. Merchant ,  Ramachandran Muralidhar

    发明人： Leo Mathew ,  Dharmesh Jawarani ,  Tushar P. Merchant ,  Ramachandran Muralidhar

    IPC分类号： H01L21/44

    CPC分类号： H01L45/1675 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/126 ,  H01L45/144

    摘要： A method for forming a phase change memory cell (PCM) includes forming a heater for the phase change memory and forming a phase change structure electrically coupled to the heater. The forming a heater includes siliciding a material including silicon to form a silicide structure, wherein the heater includes at least a portion of the silicide structure. The phase change structure exhibits a first resistive value when in a first phase state and exhibits a second resistive value when in a second phase state. The silicide structure produces heat when current flows through the silicide structure for changing the phase state of the phase change structure.

    摘要翻译： 形成相变存储单元（PCM）的方法包括形成用于相变存储器的加热器，并形成电耦合到加热器的相变结构。 形成加热器包括将包括硅的材料硅化以形成硅化物结构，其中加热器包括至少一部分硅化物结构。 当处于第一相位状态时，相变结构呈现第一电阻值，并且当处于第二相位状态时呈现第二电阻值。 当电流流过硅化物结构以改变相变结构的相位状态时，硅化物结构产生热量。

    FinFET Formation with a Thermal Oxide Spacer Hard Mask Formed from Crystalline Silicon Layer
    75.
    发明申请
    FinFET Formation with a Thermal Oxide Spacer Hard Mask Formed from Crystalline Silicon Layer 有权
    具有由结晶硅层形成的热氧化物间隔物硬掩模的FinFET形成

    公开(公告)号：US20110053361A1

    公开(公告)日：2011-03-03

    申请号：US12552774

    申请日：2009-09-02

    申请人： Ramachandran Muralidhar ,  Marwan H. Khater

    发明人： Ramachandran Muralidhar ,  Marwan H. Khater

    IPC分类号： H01L21/3065 ,  H01L21/28

    CPC分类号： H01L29/66795 ,  H01L21/3086 ,  H01L21/845

    摘要： A semiconductor process and apparatus provide a FinFET device by forming a second single crystal semiconductor layer (19) that is isolated from an underlying first single crystal semiconductor layer (17) by a buried insulator layer (18); patterning and etching the second single crystal semiconductor layer (19) to form a single crystal mandrel (42) having vertical sidewalls; thermally oxidizing the vertical sidewalls of the single crystal mandrel to grow oxide spacers (52) having a substantially uniform thickness; selectively removing any remaining portion of the single crystal mandrel (42) while substantially retaining the oxide spacers (52); and selectively etching the first single crystal semiconductor layer (17) using the oxide spacers (52) to form one or more FinFET channel regions (92).

    摘要翻译： 半导体工艺和装置通过形成通过掩埋绝缘体层（18）与下层第一单晶半导体层（17）隔离的第二单晶半导体层（19）来提供FinFET器件; 图案化和蚀刻第二单晶半导体层（19）以形成具有垂直侧壁的单晶心轴（42）; 热氧化单晶心轴的垂直侧壁以生长具有基本均匀厚度的氧化物间隔物（52）; 选择性地去除所述单晶心轴（42）的任何剩余部分，同时基本上保持所述氧化物间隔物（52）; 以及使用所述氧化物间隔物（52）选择性地蚀刻所述第一单晶半导体层（17）以形成一个或多个FinFET沟道区域（92）。

    Phase change memory structures including pillars
    77.
    发明授权
    Phase change memory structures including pillars 有权
    相变记忆结构，包括支柱

    公开(公告)号：US07719039B2

    公开(公告)日：2010-05-18

    申请号：US11864257

    申请日：2007-09-28

    申请人： Ramachandran Muralidhar ,  Tushar P. Merchant ,  Rajesh A. Rao

    发明人： Ramachandran Muralidhar ,  Tushar P. Merchant ,  Rajesh A. Rao

    IPC分类号： H01L29/80

    CPC分类号： H01L45/1675 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/148

    摘要： A phase change memory cell has a first electrode, a heater, a phase change material, and a second electrode. The heater is over the first electrode, and the heater includes a pillar. The phase change material is around the heater. The second electrode is electrically coupled to the phase change material. In some embodiments, a method includes forming a electrode layer over a substrate, depositing a first layer, providing nanoclusters over the first layer, and etching the first layer. The first layer comprises one of a group consisting of a heater material and a phase change material. The first layer may be etched using the nanocluster defined pattern to form pillars from the first layer.

    摘要翻译： 相变存储单元具有第一电极，加热器，相变材料和第二电极。 加热器在第一电极之上，加热器包括支柱。 相变材料在加热器周围。 第二电极电耦合到相变材料。 在一些实施例中，一种方法包括在衬底上形成电极层，沉积第一层，在第一层上提供纳米团簇，以及蚀刻第一层。 第一层包括由加热器材料和相变材料组成的组中的一个。 可以使用纳米簇限定图案蚀刻第一层，以形成来自第一层的柱。

    Process of forming an electronic device including discontinuous storage elements within a dielectric layer
    78.
    发明授权
    Process of forming an electronic device including discontinuous storage elements within a dielectric layer 有权
    在电介质层内形成包括不连续存储元件的电子器件的工艺

    公开(公告)号：US07642163B2

    公开(公告)日：2010-01-05

    申请号：US11693829

    申请日：2007-03-30

    申请人： Rajesh A. Rao ,  Tushar P. Merchant ,  Ramachandran Muralidhar ,  Gowrishankar Chindalore ,  David Sing ,  Jane Yater

    发明人： Rajesh A. Rao ,  Tushar P. Merchant ,  Ramachandran Muralidhar ,  Gowrishankar Chindalore ,  David Sing ,  Jane Yater

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28282 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/7881

    摘要： An electronic device can include a nonvolatile memory cell having DSEs within a dielectric layer. In one aspect, a process of forming the electronic device can include implanting and nucleating a first charge-storage material to form DSEs. The process can also include implanting a second charge-storage material and growing the DSEs such that the DSEs include the first and second charge-storage material. In another aspect, a process of forming the electronic device can include forming a semiconductor layer over a dielectric layer, implanting a charge-storage material, and annealing the dielectric layer. After annealing, substantially none of the charge-storage material remains within a denuded zone within the dielectric layer. In a third aspect, within a dielectric layer, a first set of DSEs can be spaced apart from a second set of DSEs, wherein substantially no DSEs lie between the first set of DSEs and the second set of DSEs.

    摘要翻译： 电子设备可以包括在电介质层内具有DSE的非易失性存储单元。 一方面，形成电子器件的方法可以包括将第一电荷存储材料植入和成核以形成DSE。 该过程还可以包括植入第二电荷储存材料并生长DSE，使得DSE包括第一和第二电荷存储材料。 在另一方面，形成电子器件的工艺可以包括在电介质层上形成半导体层，注入电荷存储材料，以及退火介电层。 在退火之后，基本上没有一种电荷存储材料保留在电介质层内的裸露区域内。 在第三方面，在介电层内，第一组DSE可以与第二组DSE间隔开，其中基本上没有DSE位于第一组DSE和第二组DSE之间。

    Method of making a non-volatile memory device
    79.
    发明授权
    Method of making a non-volatile memory device 有权
    制造非易失性存储器件的方法

    公开(公告)号：US07557008B2

    公开(公告)日：2009-07-07

    申请号：US11625882

    申请日：2007-01-23

    申请人： Rajesh Rao ,  Ramachandran Muralidhar

    发明人： Rajesh Rao ,  Ramachandran Muralidhar

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/7881

    摘要： A method forms a nonvolatile memory device using a semiconductor substrate. A charge storage layer is formed overlying the semiconductor substrate and a layer of gate material is formed overlying the charge storage layer to form a control gate electrode. A protective layer overlies the layer of gate material. Dopants are implanted into the semiconductor substrate and are self-aligned to the control gate electrode on at least one side of the control gate electrode to form a source and a drain in the semiconductor substrate on opposing sides of the control gate electrode. The protective layer prevents the dopants from penetrating into the control gate electrode. The protective layer that overlies the layer of gate material is removed. Electrical contact is made to the control gate electrode, the source and the drain. In one form a select gate is also provided in the memory device.

    摘要翻译： 一种方法形成使用半导体衬底的非易失性存储器件。 形成覆盖在半导体衬底上的电荷存储层，并且形成覆盖电荷存储层的栅极材料层以形成控制栅电极。 保护层覆盖栅极材料层。 将掺杂剂注入到半导体衬底中，并且在控制栅电极的至少一侧上与控制栅电极自对准，以在控制栅电极的相对侧上的半导体衬底中形成源极和漏极。 保护层防止掺杂剂渗入控制栅电极。 覆盖栅极材料层的保护层被去除。 与控制栅电极，源极和漏极电接触。 在一种形式中，选择栅极也被提供在存储器件中。

    Self-aligned split gate memory cell and method of forming
    80.
    发明授权
    Self-aligned split gate memory cell and method of forming 有权
    自对准分离栅极存储单元及其形成方法

    公开(公告)号：US07528047B2

    公开(公告)日：2009-05-05

    申请号：US11759593

    申请日：2007-06-07

    申请人： Rajesh A. Rao ,  Tushar P. Merchant ,  Ramachandran Muralidhar ,  Lakshmanna Vishnubhotla

    发明人： Rajesh A. Rao ,  Tushar P. Merchant ,  Ramachandran Muralidhar ,  Lakshmanna Vishnubhotla

    IPC分类号： H01L21/336

    CPC分类号： H01L29/792 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/42332

    摘要： A method of forming a split gate memory device using a semiconductor layer includes patterning an insulating layer to leave a pillar thereof. A gate dielectric is formed over the semiconductor layer. A charge storage layer is formed over the gate dielectric and along first and second sides of the pillar. A gate material layer is formed over the gate dielectric and pillar. An etch is performed to leave a first portion of the gate material laterally adjacent to a first side of the pillar and over a first portion of the charge storage layer that is over the gate dielectric to function as a control gate of the memory device and a second portion of the gate material laterally adjacent to a second side of the pillar and over a second portion of the charge storage layer that is over the gate dielectric to function as a select gate.

    摘要翻译： 使用半导体层形成分离栅极存储器件的方法包括图案化绝缘层以留下其柱。 在半导体层上形成栅极电介质。 电荷存储层形成在栅极电介质上并沿着柱的第一和第二侧。 栅极材料层形成在栅极电介质和支柱上。 执行蚀刻以将栅极材料的第一部分横向邻近柱的第一侧并且位于栅极电介质上方的电荷存储层的第一部分上，以用作存储器件的控制栅极，并且 栅极材料的第二部分横向邻近柱的第二侧，并且位于栅极电介质上方的电荷存储层的第二部分上，用作选择栅极。