公开(公告)号：US20080087457A1

公开(公告)日：2008-04-17

申请号：US11951646

申请日：2007-12-06

申请人： Anand Haridass ,  Andreas Huber ,  Bao Truong ,  Roger Weekly

发明人： Anand Haridass ,  Andreas Huber ,  Bao Truong ,  Roger Weekly

IPC分类号： H05K7/06

CPC分类号： H01L23/50 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  Y10T29/49155 ,  Y10T29/49163 ,  H01L2924/00

摘要： A mechanism for reducing the vertical cross-talk interference experienced in signal lines due to the inductive affects from signal lines in other signal planes of a multi-layer ceramic package is provided. With the apparatus and method, one or more vias in the multi-layer ceramic package may be removed from the structure to provide area through which an offset of the signal lines may pass. Because these offsets of the signal lines exist in parallel planes above or below each other, with no ground lines existing directly between these signal line offsets, a capacitive cross-talk is introduced into the signal lines. This capacitive cross-talk is opposite in polarity to the inductive cross-talk already experienced by the signal lines. As a result, the capacitive cross-talk tends to negate or reduce the inductive cross-talk thereby reducing the far end noise in the signal line.

公开(公告)号：US20080012583A1

公开(公告)日：2008-01-17

申请号：US11456658

申请日：2006-07-11

申请人： JEAN AUDET ,  Louis B. Capps ,  Glenn G. Daves ,  Anand Haridass ,  Ronald E. Newhart ,  Michael J. Shapiro

发明人： JEAN AUDET ,  Louis B. Capps ,  Glenn G. Daves ,  Anand Haridass ,  Ronald E. Newhart ,  Michael J. Shapiro

IPC分类号： G01R27/08 ,  G01R31/26

CPC分类号： G06F1/3203 ,  G06F1/26 ,  G06F1/3296 ,  H01L23/50 ,  H01L2924/0002 ,  Y02D10/172 ,  H01L2924/00

摘要： A reduced number of voltage regulator modules provides a reduced number of supply voltages to the package. The package includes a voltage plane for each of the voltage regulator modules. Each core or other component on the die is tied to a switch on the package, and each switch is electrically connected to all of the voltage planes. A wafer-level test determines a voltage that optimizes performance of each core or other component. Given these voltage values, an engineer may determine voltage settings for the voltage regulator modules and which cores are to be connected to which voltage regulator modules. A database stores voltage setting data, such as the optimal voltage for each component, switch values, or voltage settings for each voltage regulator module. An engineering wire may permanently set each switch to customize the voltage supply to each core or other component.

摘要翻译： 减少数量的电压调节器模块为封装提供了减少的电源电压数量。 该封装包括用于每个电压调节器模块的电压平面。 管芯上的每个核心或其他部件连接到封装上的开关，并且每个开关电连接到所有电压平面。 晶圆级测试确定优化每个核心或其他组件的性能的电压。 给定这些电压值，工程师可以确定电压调节器模块的电压设置以及要连接到哪些电压调节器模块的哪些核心。 数据库存储电压设置数据，例如每个组件的最佳电压，开关值或每个电压调节器模块的电压设置。 工程线可以永久地设置每个开关以定制每个芯或其他部件的电压供应。

公开(公告)号：US20070250796A1

公开(公告)日：2007-10-25

申请号：US11379446

申请日：2006-04-20

申请人： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Roger Weekly

发明人： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Roger Weekly

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F2217/78 ,  Y02E60/76 ,  Y04S40/22

摘要： A method for designing a power distribution system including: receiving a cross section file that contains the layout of a PCB including a location of one or more power sinks and sources on the PCB; creating an initial power distribution system; evaluating the initial power distribution system against a cost function; creating a new power distribution system; evaluating the new power distribution system against the cost function; determining if the cost function associated with the new power distribution system is equal to or greater than a stop criterion; and creating another new power distribution system if the cost function associated with the new power distribution system is greater than the stop criterion.

摘要翻译： 一种用于设计配电系统的方法，包括：接收包含PCB的布局的横截面文件，所述布局包括PCB上的一个或多个电源和源的位置; 创建初始配电系统; 根据成本函数评估初始配电系统; 建立新的配电系统; 根据成本函数评估新的配电系统; 确定与新配电系统相关联的成本函数是否等于或大于停止准则; 并且如果与新配电系统相关联的成本函数大于停止标准，则创建另一新的配电系统。

公开(公告)号：US20070239386A1

公开(公告)日：2007-10-11

申请号：US11278303

申请日：2006-03-31

申请人： Louis Capps ,  Anand Haridass ,  Ronald Newhart ,  Michael Shapiro

发明人： Louis Capps ,  Anand Haridass ,  Ronald Newhart ,  Michael Shapiro

IPC分类号： G06F19/00

CPC分类号： G01R31/2868

摘要： A computer implemented method, data processing system, and computer usable code are provided for burn-in testing of a multiprocessor. A process identifies a power management data set for a plurality of processor cores associated with the multiprocessor. The process selects one or more of the plurality of processor cores to form a selected set of processor cores based upon the power management data set. The process initiates a burn-in test across the selected set of processor cores. In response to a determination that all processor cores in the plurality of processor cores have not been selected, the process repeats the above selecting and initiating steps until all the processor cores have been selected.

摘要翻译： 提供计算机实现的方法，数据处理系统和计算机可用代码用于多处理器的老化测试。 过程识别与多处理器相关联的多个处理器核心的功率管理数据集。 该过程基于电源管理数据集选择多个处理器核中的一个或多个来形成选定的一组处理器核。 该过程在所选的一组处理器核心上启动老化测试。 响应于确定多个处理器核心中的所有处理器核心未被选择，该过程重复上述选择和启动步骤，直到所有处理器核心已被选择为止。

公开(公告)号：US07268570B1

公开(公告)日：2007-09-11

申请号：US11426646

申请日：2006-06-27

申请人： Jean Audet ,  Louis B. Capps, Jr. ,  Glenn G. Daves ,  Joanne Ferris ,  Anand Haridass ,  Ronald E. Newhart ,  Michael J. Shapiro

发明人： Jean Audet ,  Louis B. Capps, Jr. ,  Glenn G. Daves ,  Joanne Ferris ,  Anand Haridass ,  Ronald E. Newhart ,  Michael J. Shapiro

IPC分类号： G01R31/02

CPC分类号： G01R31/2855

摘要： An apparatus and method for providing a multi-core integrated circuit chip that reduces the cost of the package and board while optimizing performance of the cores for use with a single voltage plane. The apparatus and method of the illustrative embodiments make use of a dynamic burn-in technique that optimizes all of the cores on the chip to run at peak performance at a single voltage. Each core is burned-in with a customized burn-in voltage that provides uniform power and performance across the whole chip. This results in a higher burn-in yield and lower overall power in the integrated circuit chip. The optimization of the cores to run at peak performance at a single voltage is achieved through use of the negative bias temperature instability affects on the cores imparted by the burn-in voltages applied.

摘要翻译： 一种用于提供多核集成电路芯片的装置和方法，其降低了封装和板的成本，同时优化用于单个电压平面的芯的性能。 说明性实施例的装置和方法使用动态老化技术，其优化芯片上的所有核心以在单个电压下以峰值性能运行。 每个核心都具有定制的老化电压，可在整个芯片上提供均匀的功率和性能。 这导致集成电路芯片中更高的老化成本和更低的总功率。 通过使用负偏置温度不稳定性影响由所施加的老化电压施加的磁芯，可以实现在单电压下以峰值性能运行的磁芯的优化。

公开(公告)号：US08018837B2

公开(公告)日：2011-09-13

申请号：US12635121

申请日：2009-12-10

申请人： Wiren D. Becker ,  Daniel M. Dreps ,  Frank D. Ferraiolo ,  Anand Haridass ,  Robert J. Reese

发明人： Wiren D. Becker ,  Daniel M. Dreps ,  Frank D. Ferraiolo ,  Anand Haridass ,  Robert J. Reese

IPC分类号： G01R31/08

CPC分类号： H01L22/22 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.

摘要翻译： 一种用于管理用于芯片的一组信号路径的方法，装置和计算机指令。 检测用于芯片的信号路径集合内的有缺陷的信号路径。 信号通过一组信号路径重新路由，使得有缺陷的信号路径从信号路径集合中移除，并使用信号路径组中的剩余数据信号路径发送信号，并且响应于检测到的信号路径 有缺陷的信号路径。

公开(公告)号：US07930129B2

公开(公告)日：2011-04-19

申请号：US12114032

申请日：2008-05-02

申请人： Louis Bennie Capps, Jr. ,  Anand Haridass ,  Ronald Edward Newhart ,  Michael J. Shapiro

发明人： Louis Bennie Capps, Jr. ,  Anand Haridass ,  Ronald Edward Newhart ,  Michael J. Shapiro

IPC分类号： G01R31/00 ,  G01R21/00

CPC分类号： G01R31/2868

摘要： A computer implemented method, data processing system, and computer usable code are provided for burn-in testing of a multiprocessor. A process identifies a power management data set for a plurality of processor cores associated with the multiprocessor. The process selects one or more of the plurality of processor cores to form a selected set of processor cores based upon the power management data set. The process initiates a burn-in test across the selected set of processor cores. In response to a determination that all processor cores in the plurality of processor cores have not been selected, the process repeats the above selecting and initiating steps until all the processor cores have been selected.

摘要翻译： 提供计算机实现的方法，数据处理系统和计算机可用代码用于多处理器的老化测试。 过程识别与多处理器相关联的多个处理器核心的功率管理数据集。 该过程基于电源管理数据集选择多个处理器核中的一个或多个来形成选定的一组处理器核。 该过程在所选的一组处理器核心上启动老化测试。 响应于确定多个处理器核心中的所有处理器核心未被选择，该过程重复上述选择和启动步骤，直到所有处理器核心已被选择为止。

公开(公告)号：US07721119B2

公开(公告)日：2010-05-18

申请号：US11466891

申请日：2006-08-24

申请人： Louis Bennie Capps, Jr. ,  Warren D. Dyckman ,  Joanne Ferris ,  Anand Haridass ,  James Douglas Jordan ,  Ronald Edward Newhart ,  Michael Richard Ouellette ,  Michael Jay Shapiro

发明人： Louis Bennie Capps, Jr. ,  Warren D. Dyckman ,  Joanne Ferris ,  Anand Haridass ,  James Douglas Jordan ,  Ronald Edward Newhart ,  Michael Richard Ouellette ,  Michael Jay Shapiro

IPC分类号： G06F1/00

CPC分类号： G06F1/26

摘要： A system and method to optimize multi-core microprocessor performance using voltage offsets is presented. A multi-core device tests each of its processor cores in order to identify each processor core's optimum supply voltage. In turn, the device configures voltage offset networks for each processor core based upon each processor core's identified optimum supply voltage. As a result, the offset voltages produced by the voltage offset networks are subtracted from the multi-core device's main voltage, which results in the voltage offset networks supplying optimum supply voltages to each processor core. The voltage offset networks may include fuses to generate a fixed voltage offset, or the voltage offset networks may include a control circuit to dynamically adjust voltage offsets during the multi-core device's operation.

摘要翻译： 提出了使用电压偏移来优化多核微处理器性能的系统和方法。 多核设备测试每个处理器内核，以便识别每个处理器内核的最佳电源电压。 反过来，该设备基于每个处理器核心的所识别的最佳电源电压来配置每个处理器核心的电压偏移网络。 结果，从多核设备的主电压中减去由电压偏移网络产生的偏移电压，这导致电压偏移网络向每个处理器核提供最佳电源电压。 电压偏移网络可以包括熔丝以产生固定的电压偏移，或者电压偏移网络可以包括在多核装置的操作期间动态地调节电压偏移的控制电路。

公开(公告)号：US07614141B2

公开(公告)日：2009-11-10

申请号：US11355713

申请日：2006-02-16

申请人： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Roger D. Weekly

发明人： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Roger D. Weekly

IPC分类号： H01K3/10

CPC分类号： H05K1/162 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/09609 ,  H05K2201/09627 ,  Y10T29/49117 ,  Y10T29/49155 ,  H01L2924/00

摘要： A low inductance via arrangement for multilayer ceramic (MLC) substrates is provided. With the MLC substrate and via arrangement of the illustrative embodiments, the via-field inductance for a given contact pad array is reduced. This reduction is achieved by the introduction of T-jogs and additional vias. These T-jogs and additional vias form additional current paths that cause additional parallel inductances that reduce the via-field inductance. In one illustrative embodiment, the additional T-jogs and vias are added to a center portion of a contact pad array. The T-jogs are comprised of two jogs in a wiring layer of the MLC, each jog being toward a via associated with an adjacent contact pad in the contact pad array. These additional T-jogs and vias form additional current loops parallel to the existing ones which thus, reduce the total inductance of the via-field.

摘要翻译： 提供了一种用于多层陶瓷（MLC）衬底的低电感通孔布置。 通过MLC衬底和示例性实施例的通孔布置，给定接触焊盘阵列的通孔电感减小。 这种减少是通过引入T-jogs和附加通孔来实现的。 这些T形点动和附加通孔形成额外的电流路径，从而产生额外的并联电感，从而减小通路电感。 在一个说明性实施例中，附加的T形点动和通孔被添加到接触焊盘阵列的中心部分。 T-jogs由MLC的布线层中的两个点动组成，每个点动都朝向与接触垫阵列中的相邻接触焊盘相关联的通孔。 这些额外的T形点动和通孔形成与现有循环平行的额外的电流回路，从而减小通孔的总电感。

公开(公告)号：US20090031270A1

公开(公告)日：2009-01-29

申请号：US11829179

申请日：2007-07-27

申请人： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Roger D. Weekly

发明人： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Roger D. Weekly

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  H05K1/0216 ,  H05K1/115 ,  H05K3/0005 ,  H05K2201/09636

摘要： A design method and system for minimizing blind via current loops provides for improvement of electrical interconnect structure design without requiring extensive electromagnetic analysis. Other vias in the vicinity of a blind via carrying a critical signal are checked for suitability to conduct return current corresponding to the critical signal that is disrupted by the transition from a layer between two metal planes to another layer. The distance to the return current via(s) is checked and the design is adjusted to reduce the distance if the distance is greater than a specified threshold. If the blind via transition is to an external layer, suitable vias connect the reference plane at the internal end of the blind via to an external terminal. If the transition is between internal layers, suitable vias are vias that connect the two reference planes surrounding the reference plane traversed by the blind via.

摘要翻译： 用于最小化盲通过电流回路的设计方法和系统提供了电互连结构设计的改进，而不需要广泛的电磁分析。 检查通过携带关键信号的盲目附近的其他通孔是否​​适合于进行对应于由两个金属平面之间的层到另一层之间的过渡而被破坏的关键信号的返回电流。 检查通过（s）的返回电流的距离，并且如果距离大于指定的阈值，则设计被调整以减小距离。 如果盲目通过转换到外部层，合适的通孔将盲通孔内部的参考平面连接到外部端子。 如果过渡在内层之间，合适的通孔是连接围绕由盲孔通过的参考平面的两个参考平面的通孔。