公开(公告)号：US20100118591A1

公开(公告)日：2010-05-13

申请号：US12593423

申请日：2008-01-17

申请人： Tadahiko Sugibayashi

发明人： Tadahiko Sugibayashi

IPC分类号： G11C11/00 ,  G11C7/10

CPC分类号： G11C13/0007 ,  G11C7/04 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/32 ,  G11C2213/34 ,  H01L27/101

摘要： A semiconductor integrated circuit includes: an oxide resistance change element, a constant current source circuit supplying a write current to the oxide resistance change element, and a voltage clamper clamping a voltage in a path in which a write current flows. The voltage clamper is arranged in parallel with the path between the constant current source circuit and the oxide resistance change element.

摘要翻译： 半导体集成电路包括：氧化物电阻变化元件，向氧化物电阻变化元件提供写入电流的恒定电流源电路，以及夹持写入电流流动的路径中的电压的电压钳位器。 电压钳位器与恒流源电路和氧化物电阻变化元件之间的路径平行布置。

公开(公告)号：US20090141540A1

公开(公告)日：2009-06-04

申请号：US11887631

申请日：2006-03-23

申请人： Sadahiko Miura ,  Tadahiko Sugibayashi ,  Tetsuhiro Suzuki

发明人： Sadahiko Miura ,  Tadahiko Sugibayashi ,  Tetsuhiro Suzuki

IPC分类号： G11C11/02 ,  G11C11/14 ,  G11C11/416

CPC分类号： G11C11/1657 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  H01L43/08

摘要： MRAM includes a first wiring, a second wiring, and a memory cell. The first wiring extends to a first direction, and the second wiring extends to a second direction. The memory cell includes a free magnetic layer in which a plurality of magnetic layers coupled anti-ferromagnetically through non-magnetic layers are laminated, and is provided at an intersection of the first and second wirings. The magnetization direction of the free magnetic layer is different from the first and second directions. The writing method includes (a) reading a first data stored in the memory cell; (b) comparing a second data to be written to the memory cell and the first data; and (c) changing a direction of a first write current supplied to the first wiring and a direction of the second write current to be supplied to the second wiring, when the first data and second data are different.

摘要翻译： MRAM包括第一布线，第二布线和存储单元。 第一布线延伸到第一方向，第二布线延伸到第二方向。 存储单元包括自由磁性层，其中层叠有反铁磁性地通过非磁性层耦合的多个磁性层，并且设置在第一和第二布线的交叉点。 自由磁性层的磁化方向与第一和第二方向不同。 写入方法包括（a）读取存储在存储单元中的第一数据; （b）将待写入的第二数据与所述第一数据进行比较; 以及（c）当第一数据和第二数据不同时，改变提供给第一布线的第一写入电流的方向和要提供给第二布线的第二写入电流的方向。

公开(公告)号：US6104628A

公开(公告)日：2000-08-15

申请号：US377162

申请日：1999-08-19

申请人： Tadahiko Sugibayashi

发明人： Tadahiko Sugibayashi

IPC分类号： G06F12/08 ,  G06F15/78 ,  G11C5/02 ,  H01L21/822 ,  H01L27/04

CPC分类号： G11C5/025 ,  G06F12/0893 ,  G06F15/78 ,  H01L2224/05554

摘要： An integrated-circuit device comprises a combination of a microprocessor in the form of a circuit cell having a prescribed shape as an existing microprocessor and cache memories and a tag memory each in the form of a circuit cell. The tag memory have the same row addresses as the cache memories, and some of the row addresses are converted to column addresses. The tag memory is of a structure in which a basic structure similar to a conventional structure is divided into a plurality of parts in one of x and y directions, and the parts are arrayed in the other of the x and y directions. The tag memory thus shaped can be placed in a dead space on a circuit board, and hence an undesirable dead space can be eliminated from the integrated-circuit device.

摘要翻译： 集成电路装置包括具有作为现有微处理器的规定形状的电路单元形式的微处理器和高速缓冲存储器以及电路单元形式的标签存储器的组合。 标签存储器具有与高速缓存存储器相同的行地址，并且一些行地址被转换为列地址。 标签存储器是将与传统结构类似的基本结构在x和y方向中的一个方向上划分成多个部分的结构，并且这些部分被排列在x和y方向中的另一个中。 因此，如此形成的标签存储器可以放置在电路板上的死空间中，因此可以从集成电路装置中消除不期望的死区。

公开(公告)号：US5406526A

公开(公告)日：1995-04-11

申请号：US129363

申请日：1993-09-30

申请人： Tadahiko Sugibayashi ,  Mamoru Fujita ,  Isao Naritake

发明人： Tadahiko Sugibayashi ,  Mamoru Fujita ,  Isao Naritake

IPC分类号： G11C11/408 ,  G11C11/4091 ,  G11C8/00

CPC分类号： G11C11/408 ,  G11C11/4091

摘要： A dynamic random access memory device selects a row of memory cells from a plurality of memory cell sub-arrays with main word lines and sub-word lines for a data access, and data bits read out from the row of memory cells are amplified by a sense amplifier circuit array, wherein a row block address decoder and a column block address decoder supply a first enable signal and a second enable signal to a row of memory cell sub-arrays and a column of memory cell sub-arrays so that only one of the sense amplifier circuit arrays is powered for the amplification, thereby decreasing peak current consumed by the sense amplifier circuit arrays.

摘要翻译： 动态随机存取存储器装置从具有用于数据存取的主字线和子字线的多个存储单元子阵列中选择一行存储单元，从存储单元行读出的数据位由 读出放大器电路阵列，其中行块地址解码器和列块地址解码器向一行存储器单元子阵列和一列存储器单元子阵列提供第一使能信号和第二使能信号，使得仅一个 感测放大器电路阵列被供电用于放大，从而减少由读出放大器电路阵列消耗的峰值电流。

公开(公告)号：US5352935A

公开(公告)日：1994-10-04

申请号：US955287

申请日：1992-10-01

申请人： Ryuji Yamamura ,  Tadahiko Sugibayashi ,  Takahiro Hara

发明人： Ryuji Yamamura ,  Tadahiko Sugibayashi ,  Takahiro Hara

IPC分类号： G11C11/413 ,  G05F1/46 ,  G05F1/56 ,  G05F3/24 ,  G11C11/407 ,  H03K17/24

CPC分类号： G05F1/465

摘要： A semiconductor integrated circuit device has a first internal voltage controlling circuit which lowers an external power source voltage and produces a predetermined internal power source voltage. The device further has a second internal voltage controlling circuit formed by an internal-voltage drop detection circuit for detecting the lowering of the internal power source voltage from a predetermined reference voltage and a switching circuit for causing the external power source voltage to be directly connected to an internal voltage output terminal based on an output from the internal-voltage drop detection circuit. The internal power source voltage is maintained close to the required value thereby preventing a deterioration of circuit performance even when the external power source voltage drops close to the internal power source voltage.

摘要翻译： 半导体集成电路器件具有第一内部电压控制电路，其降低外部电源电压并产生预定的内部电源电压。 该装置还具有由内部电压降检测电路形成的第二内部电压控制电路，用于检测来自预定参考电压的内部电源电压的降低以及用于使外部电源电压直接连接到 基于来自内部电压降检测电路的输出的内部电压输出端子。 内部电源电压保持接近所需值，从而即使当外部电源电压下降到接近内部电源电压时也防止电路性能的劣化。

公开(公告)号：US5272673A

公开(公告)日：1993-12-21

申请号：US824206

申请日：1992-01-22

申请人： Tadahiko Sugibayashi

发明人： Tadahiko Sugibayashi

IPC分类号： G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C29/00 ,  G11C29/02 ,  G11C29/04 ,  G11C29/50

CPC分类号： G11C29/025 ,  G11C29/02 ,  G11C29/50 ,  G11C11/401

摘要： A dynamic random access memory device can enter a diagnostic mode of operation to see whether or not undesirable short-circuit takes place in a word line and/or a control signal line for transfer gates between bit lines and a sense amplifier unit, and a built-in testing operation discriminating unit discriminates the testing operation on the word lines and the control signal lines from other testing operations for causing a power supply system to interrupt electric power to a row address decoder unit and a driver unit for the control signal lines so that voltage level on a word line and/or a control signal line is rapidly decayed due to the short-circuit, thereby screening out the defective products before the delivery from the manufacturer.

摘要翻译： 动态随机存取存储器件可以进入诊断操作模式，以查看在位线和/或读出放大器单元之间的传输门的字线和/或控制信号线中是否发生不期望的短路，以及构建 在测试操作识别单元鉴别来自其他测试操作的字线和控制信号线的测试操作，以使电源系统中断对行地址解码器单元的电力和用于控制信号线的驱动器单元，使得 字线和/或控制信号线上的电压电平由于短路而迅速衰减，从而在从制造商传送之前筛选出有缺陷的产品。

公开(公告)号：US07817462B2

公开(公告)日：2010-10-19

申请号：US11887631

申请日：2006-03-23

申请人： Sadahiko Miura ,  Tadahiko Sugibayashi ,  Tetsuhiro Suzuki

发明人： Sadahiko Miura ,  Tadahiko Sugibayashi ,  Tetsuhiro Suzuki

IPC分类号： G11C11/00

CPC分类号： G11C11/1657 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  H01L43/08

摘要： MRAM includes a first wiring, a second wiring, and a memory cell. The first wiring extends to a first direction, and the second wiring extends to a second direction. The memory cell includes a free magnetic layer in which a plurality of magnetic layers coupled anti-ferromagnetically through non-magnetic layers are laminated, and is provided at an intersection of the first and second wirings. The magnetization direction of the free magnetic layer is different from the first and second directions. The writing method includes (a) reading a first data stored in the memory cell; (b) comparing a second data to be written to the memory cell and the first data; and (c) changing a direction of a first write current supplied to the first wiring and a direction of the second write current to be supplied to the second wiring, when the first data and second data are different.

摘要翻译： MRAM包括第一布线，第二布线和存储单元。 第一布线延伸到第一方向，第二布线延伸到第二方向。 存储单元包括自由磁性层，其中层叠有反铁磁性地通过非磁性层耦合的多个磁性层，并且设置在第一和第二布线的交叉点。 自由磁性层的磁化方向与第一和第二方向不同。 写入方法包括（a）读取存储在存储单元中的第一数据; （b）将待写入的第二数据与所述第一数据进行比较; 以及（c）当第一数据和第二数据不同时，改变提供给第一布线的第一写入电流的方向和要提供给第二布线的第二写入电流的方向。

公开(公告)号：US20060157802A1

公开(公告)日：2006-07-20

申请号：US10490598

申请日：2002-09-24

申请人： Toshitsugu Sakamoto ,  Masakazu Aono ,  Tsuyoshi Hasegawa ,  Tomonbu Nakayama ,  Kazuya Terabe ,  Hisao Kawaura ,  Tadahiko Sugibayashi

发明人： Toshitsugu Sakamoto ,  Masakazu Aono ,  Tsuyoshi Hasegawa ,  Tomonbu Nakayama ,  Kazuya Terabe ,  Hisao Kawaura ,  Tadahiko Sugibayashi

IPC分类号： H01L29/76

CPC分类号： G11C13/0011 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/72 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/085 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/16 ,  H01L45/1633

摘要： The present invention relates to a transistor for selecting a storage cell and a switch using a solid electrolyte. In a storage cell, a metal is stacked on a drain diffusion layer of a field-effect transistor formed on a semiconductor substrate surface. The solid electrolyte using the metal as a carrier is stacked on the metal. The solid electrolyte contacts with the metal via a gap, and the metal is connected to a common grounding conductor. A source of the field-effect transistor is connected to a column address line, and a gate of the field-effect transistor is connected to a row address line.

摘要翻译： 本发明涉及用于选择存储单元的晶体管和使用固体电解质的开关。 在存储单元中，在形成在半导体衬底表面上的场效应晶体管的漏极扩散层上堆叠金属。 使用金属作为载体的固体电解质堆叠在金属上。 固体电解质通过间隙与金属接触，并且金属连接到公共接地导体。 场效应晶体管的源极连接到列地址线，并且场效应晶体管的栅极连接到行地址线。

公开(公告)号：US20060056250A1

公开(公告)日：2006-03-16

申请号：US10512545

申请日：2003-04-21

申请人： Sadahiko Miura ,  Tadahiko Sugibayashi ,  Hideaki Numata ,  Kiyotaka Tsuji

发明人： Sadahiko Miura ,  Tadahiko Sugibayashi ,  Hideaki Numata ,  Kiyotaka Tsuji

IPC分类号： G11C7/00

CPC分类号： H01L27/228 ,  B82Y10/00 ,  G11C11/16

摘要： A technology for eliminating the defects in a tunnel insulation film of magnetic tunnel junction and for suppressing generation of a defective bit in an MRAM using magnetic tunnel junction in a memory. The magnetic memory includes a substrate, an interlayer insulation film covering the upper surface side of the substrate, memory cells, and plugs penetrating the interlayer insulation film. The memory cell includes a first magnetic layer formed on the upper surface side of the interlayer insulation film, a tunnel insulation layer formed on the first magnetic layer, and a second magnetic layer formed on the tunnel insulation layer. The plug is connected electrically with the first magnetic layer. The tunnel current passing part of the tunnel insulation layer located between the first and second magnetic layers is arranged, at least partially, so as not to overlap the plug in the direction perpendicular to the surface of the substrate.

摘要翻译： 一种用于消除磁隧道结隧道绝缘膜中的缺陷并用于抑制在存储器中使用磁性隧道结的MRAM中的有缺陷位的产生的技术。 磁性存储器包括基板，覆盖基板的上表面侧的层间绝缘膜，存储单元和穿透层间绝缘膜的插塞。 存储单元包括形成在层间绝缘膜的上表面侧的第一磁性层，形成在第一磁性层上的隧道绝缘层和形成在隧道绝缘层上的第二磁性层。 插头与第一磁性层电连接。 位于第一和第二磁性层之间的隧道绝缘层的隧道电流通过部分被布置成至少部分地不与垂直于衬底的表面的方向上的插塞重叠。

公开(公告)号：US06442742B1

公开(公告)日：2002-08-27

申请号：US09420693

申请日：1999-10-19

申请人： Tadahiko Sugibayashi

发明人： Tadahiko Sugibayashi

IPC分类号： G06F1750

CPC分类号： G06F15/7846 ,  G11C29/785 ,  G11C29/80

摘要： Semiconductor integrated circuit includes a MPU and a cache memory implemented by a plurality of DRAM macro blocks each disposed between the MPU and bonding pads of the chip. Each DRAM macro block has a redundancy function for replacing a defective row with a redundancy row of memory cells. A plurality of fuse blocks each for storing the row address of the defective row are arranged in a row, with the elongate sides of each of the fuse blocks extending parallel to the signal lines extending between the MPU and the bonding pads. The arrangement allows a large number of signal lines to pass the space between the fuse blocks, thereby allowing a smaller chip size.

摘要翻译： 半导体集成电路包括MPU和由多个DRAM宏块实现的高速缓冲存储器，每个DRAM宏块均设置在MPU和芯片的焊盘之间。 每个DRAM宏块具有用于用存储器单元的冗余行替换缺陷行的冗余功能。 用于存储有缺陷行的行地址的多个熔丝块被布置成一行，每个熔丝块的细长边平行于在MPU和焊盘之间延伸的信号线延伸。 该布置允许大量信号线通过熔丝块之间的空间，从而允许更小的芯片尺寸。