公开(公告)号：US11652005B2

公开(公告)日：2023-05-16

申请号：US17652712

申请日：2022-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chun Chen ,  Ryan Chia-Jen Chen ,  Shu-Yuan Ku ,  Ya-Yi Tsai ,  I-Wei Yang

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823828 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924

Abstract: An anchored cut-metal gate (CMG) plug, a semiconductor device including the anchored CMG plug and methods of forming the semiconductor device are disclosed herein. The method includes performing a series of etching processes to form a trench through a metal gate electrode, through an isolation region, and into a semiconductor substrate. The trench cuts-through and separates the metal gate electrode into a first metal gate and a second metal gate and forms a recess in the semiconductor substrate. Once the trench has been formed, a dielectric plug material is deposited into the trench to form a CMG plug that is anchored within the recess of the semiconductor substrate and separates the first and second metal gates. As such, the anchored CMG plug provides high levels of resistance to reduce leakage current within the semiconductor device during operation and allowing for improved V-trigger performance of the semiconductor device.

公开(公告)号：US11637206B2

公开(公告)日：2023-04-25

申请号：US17247687

申请日：2020-12-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Wei Yang ,  Chih-Chang Hung ,  Shu-Yuan Ku ,  Ryan Chia-Jen Chen ,  Ming-Ching Chang

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L27/088 ,  H01L23/532 ,  H01L29/66 ,  H01L21/033 ,  H01L21/8238 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/311

Abstract: A semiconductor device and method of forming thereof includes a first fin and a second fin each extending from a substrate. A first gate segment is disposed over the first fin and a second gate segment is disposed over the second fin. An interlayer dielectric (ILD) layer is adjacent the first gate segment and the second gate segment. A cut region (e.g., opening or gap between first gate structure and the second gate structure) extends between the first and second gate segments. The cut region has a first portion has a first width and a second portion has a second width, the second width is greater than the first width. The second portion interposes the first and second gate segments and the first portion is defined within the ILD layer.

公开(公告)号：US20230027789A1

公开(公告)日：2023-01-26

申请号：US17730797

申请日：2022-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Wei Yin ,  Yun-Chen Wu ,  Tzu-Wen Pan ,  Jih-Sheng Yang ,  Yu-Hsien Lin ,  Ryan Chia-Jen Chen

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/40 ,  H01L29/06 ,  H01L29/786 ,  H01L27/092 ,  H01L21/8238

Abstract: Improved gate structures, methods for forming the same, and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a gate structure over a semiconductor substrate, the gate structure including a high-k dielectric layer; a gate electrode over the high-k dielectric layer; a conductive cap over and in contact with the high-k dielectric layer and the gate electrode, a top surface of the conductive cap being convex; and first gate spacers on opposite sides of the gate structure, the high-k dielectric layer and the conductive cap extending between opposite sidewalls of the first gate spacers.

公开(公告)号：US11152249B2

公开(公告)日：2021-10-19

申请号：US16874677

申请日：2020-05-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jih-Jse Lin ,  Ryan Chia-Jen Chen ,  Fang-Cheng Chen ,  Ming-Ching Chang

IPC: H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L21/764 ,  H01L21/3065 ,  H01L29/78 ,  H01L21/311 ,  H01L29/165

Abstract: A method of forming a FinFET device includes following steps. A substrate is provided with a plurality of fins thereon, an isolation layer thereon covering lower portions of the fins, a plurality of dummy strips across the fins, and a dielectric layer aside the dummy strips. The dummy strips is cut to form a trench in the dielectric layer. A first insulating structure is formed in the trench, wherein first and second groups of the dummy strips are beside the first insulating structure. A dummy strip is removed from the first group of the dummy strips to form a first opening that exposes portions of the fins under the dummy strip. The portions of the fins are removed to form a plurality of second openings below the first opening, wherein each second opening has a middle-wide profile. A second insulating structure is formed in the first and second openings.

公开(公告)号：US10672613B2

公开(公告)日：2020-06-02

申请号：US16115394

申请日：2018-08-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shu-Uei Jang ,  Chien-Hua Tseng ,  Chung-Shu Wu ,  Ya-Yi Tsai ,  Ryan Chia-Jen Chen ,  An-Chyi Wei

IPC: H01L21/28 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/78 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66 ,  H01L29/06

Abstract: A method of forming a semiconductor structure includes forming a metal gate stack over a shallow trench isolation (STI) material in a semiconductor substrate, forming an interlayer dielectric over the STI material, recessing the interlayer dielectric to a height lower than a top surface of the metal gate stack, forming a helmet structure over the recessed interlayer dielectric, and after forming the helmet structure, etching the metal gate stack until reaching the STI material.

公开(公告)号：US20190229010A1

公开(公告)日：2019-07-25

申请号：US15874889

申请日：2018-01-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jih-Jse Lin ,  Ryan Chia-Jen Chen ,  Fang-Cheng Chen ,  Ming-Ching Chang

IPC: H01L21/762 ,  H01L21/8234 ,  H01L21/3065 ,  H01L21/764 ,  H01L27/088

Abstract: FinFET devices and methods of forming the same are disclosed. One of the FinFET devices includes first fins, second fins, a first gate strip, a second gate strip and a comb-like insulating structure. The first and second fins are disposed on a substrate. The first gate strip is disposed across the first fins. The second gate strip is disposed across the second fins. The comb-like insulating structure is disposed between the first gate strip and the second gate strip and has a plurality of comb tooth parts. In some embodiments, each of the comb tooth parts has a middle-wide profile.

公开(公告)号：US10269787B2

公开(公告)日：2019-04-23

申请号：US15809898

申请日：2017-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shiang-Bau Wang ,  Ming-Ching Chang ,  Shu-Yuan Ku ,  Ryan Chia-Jen Chen

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L21/027 ,  H01L21/285 ,  H01L21/311 ,  H01L21/762 ,  H01L27/088 ,  H01L29/423 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/8234

Abstract: Methods for cutting (e.g., dividing) metal gate structures in semiconductor device structures are provided. A dual layer structure can form sub-metal gate structures in a replacement gate manufacturing processes, in some examples. In an example, a semiconductor device includes a plurality of metal gate structures disposed in an interlayer dielectric (ILD) layer disposed on a substrate, an isolation structure disposed between the metal gate structures, wherein the ILD layer circumscribes a perimeter of the isolation structure, and a dielectric structure disposed between the ILD layer and the isolation structure.

公开(公告)号：US20190109126A1

公开(公告)日：2019-04-11

申请号：US16203755

申请日：2018-11-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shiang-Bau Wang ,  Ryan Chia-Jen Chen ,  Shu-Yuan Ku ,  Ming-Ching Chang

IPC: H01L27/02 ,  H01L29/06

Abstract: Methods for cutting (e.g., dividing) metal gate structures in semiconductor device structures are provided. A dual layer structure can form sub-metal gate structures in a replacement gate manufacturing processes, in some examples. In an example, a semiconductor device includes a plurality of metal gate structures disposed in an interlayer dielectric (ILD) layer disposed on a substrate, an isolation structure disposed between the metal gate structures, wherein the ILD layer circumscribes a perimeter of the isolation structure, and a dielectric structure disposed between the ILD layer and the isolation structure.