公开(公告)号：US20210305258A1

公开(公告)日：2021-09-30

申请号：US17036418

申请日：2020-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Hsu ,  Jian-Hao Chen ,  Chia-Wei Chen ,  Shan-Mei Liao ,  Hui-Chi Chen ,  Yu-Chia Liang ,  Shih-Hao Lin ,  Kuei-Lun Lin ,  Kuo-Feng Yu ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L27/11

Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

公开(公告)号：US20210098468A1

公开(公告)日：2021-04-01

申请号：US16776205

申请日：2020-01-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Lin Chen ,  Chao-Yuan Chang ,  Ping-Wei Wang ,  Fu-Kai Yang ,  Ting Fang ,  I-Wen Wu ,  Shih-Hao Lin

IPC: H01L27/11 ,  H01L29/417 ,  H01L23/522 ,  H01L29/40 ,  H01L21/02 ,  H01L21/768

Abstract: A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.

公开(公告)号：US12142684B2

公开(公告)日：2024-11-12

申请号：US18359034

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Wen Su ,  Yu-Kuan Lin ,  Chih-Chuan Yang ,  Chang-Ta Yang ,  Shih-Hao Lin

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/762

Abstract: A semiconductor device includes a memory macro having a middle strap area between edges of the memory macro and memory bit areas on both sides of the middle strap area. The memory macro includes n-type wells and p-type wells arranged alternately along a first direction with well boundaries between the adjacent n-type and p-type wells. The n-type and the p-type wells extend lengthwise along a second direction and extend continuously through the middle strap area and the memory bit areas. The memory macro includes a first dielectric layer disposed at the well boundaries in the middle strap area and the memory bit areas. From a top view, the first dielectric layer extends along the second direction and fully separates the n-type wells from the p-type wells in the middle strap area. From a cross-sectional view, the first dielectric layer vertically extends into the n-type or the p-type wells.

公开(公告)号：US20240332089A1

公开(公告)日：2024-10-03

申请号：US18741998

申请日：2024-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Jui-Lin Chen ,  Hsin-Wen Su ,  Kian-Long Lim ,  Bwo-Ning Chen ,  Chih-Hsuan Chen

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/3115 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/823468 ,  H01L21/02532 ,  H01L21/0259 ,  H01L21/31155 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/78618 ,  H01L29/78696

Abstract: Methods of forming a semiconductor device are provided. A method according to the present disclosure includes forming, over a workpiece, a dummy gate stack comprising a first semiconductor material, depositing a first dielectric layer over the dummy gate stack using a first process, implanting the workpiece with a second semiconductor material different from the first semiconductor material, annealing the dummy gate stack after the implanting, and replacing the dummy gate stack with a metal gate stack.

公开(公告)号：US12027425B2

公开(公告)日：2024-07-02

申请号：US17877221

申请日：2022-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Jui-Lin Chen ,  Hsin-Wen Su ,  Kian-Long Lim ,  Bwo-Ning Chen ,  Chih-Hsuan Chen

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/3115 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/823468 ,  H01L21/02532 ,  H01L21/0259 ,  H01L21/31155 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/78618 ,  H01L29/78696

Abstract: Methods of forming a semiconductor device are provided. A method according to the present disclosure includes forming, over a workpiece, a dummy gate stack comprising a first semiconductor material, depositing a first dielectric layer over the dummy gate stack using a first process, implanting the workpiece with a second semiconductor material different from the first semiconductor material, annealing the dummy gate stack after the implanting, and replacing the dummy gate stack with a metal gate stack.

公开(公告)号：US12022643B2

公开(公告)日：2024-06-25

申请号：US17036418

申请日：2020-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Hsu ,  Jian-Hao Chen ,  Chia-Wei Chen ,  Shan-Mei Liao ,  Hui-Chi Chen ,  Yu-Chia Liang ,  Shih-Hao Lin ,  Kuei-Lun Lin ,  Kuo-Feng Yu ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L27/11 ,  H10B10/00

CPC classification number: H10B10/12

Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

公开(公告)号：US11968817B2

公开(公告)日：2024-04-23

申请号：US17682061

申请日：2022-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Lin Chen ,  Chao-Yuan Chang ,  Ping-Wei Wang ,  Fu-Kai Yang ,  Ting Fang ,  I-Wen Wu ,  Shih-Hao Lin

IPC: H10B10/00 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L29/40 ,  H01L29/417

CPC classification number: H10B10/12 ,  H01L21/02063 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/5226 ,  H01L29/401 ,  H01L29/41791

Abstract: A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.

公开(公告)号：US11937416B2

公开(公告)日：2024-03-19

申请号：US17750649

申请日：2022-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Kian-Long Lim ,  Chih-Chuan Yang ,  Chia-Hao Pao ,  Jing-Yi Lin

IPC: H01L27/11 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10B10/00

CPC classification number: H10B10/125 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A substrate includes a first doped region having a first type dopant, and a second doped region having a second type dopant and adjacent to the first doped region. A stack is formed that includes first layers and second layers alternating with each other. The first and second layers each have a first and second semiconductor material, respectively. The second semiconductor material is different than the first semiconductor material. A mask element is formed that has an opening in a channel region over the second doped region. A top portion of the stack not covered by the mask element is recessed. The stack is then processed to form a first and a second transistors. The first transistor has a first number of first layers. The second transistor has a second number of first layers. The first number is greater than the second number.

公开(公告)号：US20230387199A1

公开(公告)日：2023-11-30

申请号：US18446665

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bwo-Ning Chen ,  Xusheng Wu ,  Pin-Ju Liang ,  Chang-Miao Liu ,  Shih-Hao Lin

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/66742 ,  H01L21/02603 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/78696

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a semiconductor stack including semiconductor layers over a substrate, wherein the semiconductor layers are separated from each other and are stacked up along a direction substantially perpendicular to a top surface of the substrate; an isolation structure around a bottom portion of the semiconductor stack and separating active regions; a metal gate structure over a channel region of the semiconductor stack and wrapping each of the semiconductor layers; a gate spacer over a source/drain (S/D) region of the semiconductor stack and along sidewalls of a top portion of the metal gate structure; and an inner spacer over the S/D region of the semiconductor stack and along sidewalls of lower portions of the metal gate structure and wrapping edge portions of each of the semiconductor layers.

公开(公告)号：US20230063098A1

公开(公告)日：2023-03-02

申请号：US17462634

申请日：2021-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Shih-Hao Lin ,  Yu-Kuan Lin

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L27/11

Abstract: A method includes providing a substrate, a source/drain (S/D) feature and semiconductor channel layers over the substrate, a high-k metal gate (HKMG) wrapping around the channel layers, a dielectric cap over the HKMG, a contact etch stop layer (CESL) over the S/D feature and on sidewalls of the dielectric cap and the HKMG, and an interlayer dielectric (ILD) layer over the CESL. The channel layers are spaced one from another along a direction perpendicular to a top surface of the substrate and connect to the S/D feature. The method further includes etching the ILD layer and the CESL to expose a top portion of the S/D feature; etching the S/D feature, resulting in a S/D contact trench, wherein a bottom surface of the S/D contact trench is below an upper surface of a bottommost layer of the channel layers; and forming a metallic contact in the S/D contact trench.