Borderless contact structures
    71.
    发明申请

    公开(公告)号:US20060024940A1

    公开(公告)日:2006-02-02

    申请号:US10710675

    申请日:2004-07-28

    IPC分类号: H01L21/44

    摘要: A borderless contact structure and method of fabricating the structure, the method including: (a) providing a substrate; (b) forming a polysilicon line on the substrate, the polysilicon line having sidewalls; (c) forming an insulating sidewall layer on the sidewalls of the polysilicon line; (d) removing a portion of the polysilicon line and a corresponding portion of the insulating sidewall layer in a contact region of the polysilicon line; and (e) forming a silicide layer on the sidewall of the polysilicon line in the contact region. Also an SRAM cell using the borderless contact structure and a method of fabricating the SRAM cell.

    MEMORY DEVICES USING CARBON NANOTUBE (CNT) TECHNOLOGIES
    73.
    发明申请
    MEMORY DEVICES USING CARBON NANOTUBE (CNT) TECHNOLOGIES 有权
    使用碳纳米管(CNT)技术的存储器件

    公开(公告)号:US20080117671A1

    公开(公告)日:2008-05-22

    申请号:US12018915

    申请日:2008-01-24

    IPC分类号: G11C11/34 G11C7/00

    摘要: Structures for memory devices. The structure includes (a) a substrate; (b) a first and second electrode regions on the substrate; and (c) a third electrode region disposed between the first and second electrode regions. In response to a first write voltage potential applied between the first and third electrode regions, the third electrode region changes its own shape, such that in response to a pre-specified read voltage potential subsequently applied between the first and third electrode regions, a sensing current flows between the first and third electrode regions. In addition, in response to a second write voltage potential being applied between the second and third electrode regions, the third electrode region changes its own shape such that in response to the pre-specified read voltage potential applied between the first and third electrode regions, said sensing current does not flow between the first and third electrode regions.

    摘要翻译: 存储器件结构。 该结构包括(a)基底; (b)基板上的第一和第二电极区域; 和(c)设置在第一和第二电极区之间的第三电极区。 响应于施加在第一和第三电极区域之间的第一写入电压电位,第三电极区域改变其自身形状,使得响应于随后施加在第一和第三电极区域之间的预先指定的读取电压电势,感测 电流在第一和第三电极区域之间流动。 此外,响应于施加在第二和第三电极区域之间的第二写入电压电位,第三电极区域改变其自身形状,使得响应于施加在第一和第三电极区域之间的预先设定的读取电压电位, 所述感测电流不在第一和第三电极区域之间流动。

    Integrated Circuit Chip Utilizing Oriented Carbon Nanotube Conductive Layers
    75.
    发明申请
    Integrated Circuit Chip Utilizing Oriented Carbon Nanotube Conductive Layers 失效
    集成电路芯片利用定向碳纳米管导电层

    公开(公告)号:US20080042287A1

    公开(公告)日:2008-02-21

    申请号:US11924894

    申请日:2007-10-26

    IPC分类号: H01L23/52

    摘要: A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least one sublayer of oriented carbon nanotubes. The conductive layer sandwich preferably contains two sublayers of carbon nanotubes, in which the carbon nanotube orientation in one sublayer is substantially perpendicular to that of the other layer. The conductive layer sandwich preferably contains one or more additional sublayers of a conductive material, such as a metal. In one embodiment, oriented carbon nanotubes are created by forming a series of parallel surface ridges, covering the top and one side of the ridges with a catalyst inhibitor, and growing carbon nanotubes horizontally from the uncovered vertical sides of the ridges. In another embodiment, oriented carbon nanotubes are grown on the surface of a conductive material in the presence of a directional flow of reactant gases and a catalyst.

    摘要翻译: 集成电路中的导电层形成为具有多个子层的夹层,包括至少一个定向碳纳米管子层。 导电层夹层优选含有碳纳米管的两个子层,其中一个子层中的碳纳米管取向基本上垂直于另一层的碳纳米管取向。 导电层夹层优选地包含一种或多种另外的导电材料的子层,例如金属。 在一个实施方案中,通过形成一系列平行的表面脊,通过用催化剂抑制剂覆盖脊的顶部和一侧并从脊的未被覆盖的垂直侧水平生长碳纳米管来产生定向碳纳米管。 在另一个实施方案中,在反应物气体和催化剂的定向流的存在下,在导电材料的表面上生长取向的碳纳米管。

    Immersion optical lithography system having protective optical coating
    76.
    发明申请
    Immersion optical lithography system having protective optical coating 失效
    具有保护性光学涂层的浸没光学光刻系统

    公开(公告)号:US20070296947A1

    公开(公告)日:2007-12-27

    申请号:US11899085

    申请日:2007-09-04

    IPC分类号: G03B27/42

    摘要: An immersion lithography system is provided which includes an optical source operable to produce light having a nominal wavelength and an optical imaging system. The optical imaging system has an optical element in an optical path from the optical source to an article to be patterned thereby. The optical element has a face which is adapted to contact a liquid occupying a space between the face and the article. The optical element includes a material which is degradable by the liquid and a protective coating which covers the degradable material at the face for protecting the face from the liquid, the protective coating being transparent to the light, stable when exposed to the light and stable when exposed to the liquid.

    摘要翻译: 提供了一种浸没光刻系统,其包括可操作以产生具有标称波长的光和光学成像系统的光源。 光学成像系统具有从光源到待图案化的制品的光路中的光学元件。 光学元件具有适于接触占据面部和制品之间的空间的液体的面。 光学元件包括可被液体降解的材料和覆盖面上的可降解材料以保护面部免受液体的保护涂层,保护涂层对于光是透明的,当暴露于光时稳定,并且当稳定时 暴露于液体。

    METHOD OF DOPING A GATE ELECTRODE OF A FIELD EFFECT TRANSISTOR
    77.
    发明申请
    METHOD OF DOPING A GATE ELECTRODE OF A FIELD EFFECT TRANSISTOR 失效
    电场效应晶体管的栅极电极的方法

    公开(公告)号:US20070228429A1

    公开(公告)日:2007-10-04

    申请号:US11757660

    申请日:2007-06-04

    IPC分类号: H01L29/78

    摘要: A method of fabricating a structure and fabricating related semiconductor transistors and novel semiconductor transistor structures. The method of fabricating the structure includes: providing a substrate having a top surface; forming an island on the top surface of the substrate, a top surface of the island parallel to the top surface of the substrate, a sidewall of the island extending between the top surface of the island and the top surface of the substrate; forming a plurality of carbon nanotubes on the sidewall of the island; and performing an ion implantation, the ion implantation penetrating into the island and blocked from penetrating into the substrate in regions of the substrate masked by the island and the carbon nanotubes.

    摘要翻译: 一种制造结构并制造相关半导体晶体管和新型半导体晶体管结构的方法。 制造该结构的方法包括:提供具有顶表面的基底; 在所述基板的顶表面上形成岛,所述岛的顶表面平行于所述基底的顶表面,所述岛的侧壁在所述岛的顶表面和所述基底的顶表面之间延伸; 在岛的侧壁上形成多个碳纳米管; 并且进行离子注入,所述离子注入在所述岛状体和所述碳纳米管所掩盖的基板的区域中贯穿所述岛并阻止其侵入所述基板。

    CMOS devices adapted to reduce latchup and methods of manufacturing the same
    80.
    发明申请
    CMOS devices adapted to reduce latchup and methods of manufacturing the same 审中-公开
    适于减少闭锁的CMOS器件及其制造方法

    公开(公告)号:US20070170517A1

    公开(公告)日:2007-07-26

    申请号:US11340342

    申请日:2006-01-26

    IPC分类号: H01L29/76

    摘要: In a first aspect, a first apparatus is provided. The first apparatus is semiconductor device that includes (1) a shallow trench isolation (STI) oxide region; (2) a first metal-oxide-semiconductor field-effect transistor (MOSFET) coupled to a first side of the STI oxide region; (3) a second MOSFET coupled to a second side of the STI oxide region, wherein portions of the first and second MOSFETs form first and second bipolar junction transistors (BJTs) which are coupled into a loop; and (4) a dopant-implanted region below the STI oxide region, wherein the dopant-implanted region forms a portion of the BJT loop and is adapted to reduce a gain of the loop. Numerous other aspects are provided.

    摘要翻译: 在第一方面中,提供了一种第一装置。 第一装置是包括(1)浅沟槽隔离(STI)氧化物区域的半导体器件; (2)耦合到所述STI氧化物区域的第一侧的第一金属氧化物半导体场效应晶体管(MOSFET); (3)耦合到所述STI氧化物区域的第二侧的第二MOSFET,其中所述第一和第二MOSFET的部分形成耦合到环路中的第一和第二双极结型晶体管(BJT); 和(4)STI氧化物区域下面的掺杂剂注入区域,其中掺杂剂注入区域形成BJT环路的一部分并且适于减小环路的增益。 提供了许多其他方面。