公开(公告)号：US20050022935A1

公开(公告)日：2005-02-03

申请号：US10929835

申请日：2004-08-30

申请人： Guy Blalock ,  Kevin Donohoe

发明人： Guy Blalock ,  Kevin Donohoe

IPC分类号： C23C16/505 ,  H01J37/32 ,  H01L21/205 ,  H01L21/302 ,  H01L21/3065 ,  H05H1/46 ,  C23F1/00

CPC分类号： H01J37/32091 ,  H01J37/321 ,  H01J37/32183 ,  H05H1/46

摘要： A plasma reactor comprises an electromagnetic energy source coupled to a radiator through first and second variable impedance networks. The plasma reactor includes a chamber having a dielectric window that is proximate to the radiator. A shield is positioned between the radiator and the dielectric window. The shield substantially covers a surface of the radiator near the dielectric window. A portion of the radiator that is not covered by the shield is proximate to a conductive wall of the chamber. Plasma reactor operation includes the following steps. A plasma is ignited in a chamber with substantially capacitive electric energy coupled from the radiator. A variable impedance network is tuned so that the capacitive electric energy coupled into the chamber is diminished. The plasma is then powered with substantially magnetic energy.

公开(公告)号：US06812160B2

公开(公告)日：2004-11-02

申请号：US09976624

申请日：2001-10-12

申请人： Werner Juengling ,  Kirk D. Prall ,  Ravi Iyer ,  Gurtej S. Sandhu ,  Guy Blalock

发明人： Werner Juengling ,  Kirk D. Prall ,  Ravi Iyer ,  Gurtej S. Sandhu ,  Guy Blalock

IPC分类号： H01L2131

CPC分类号： H01L21/7682 ,  H01L21/02115 ,  H01L21/02118 ,  H01L21/02167 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  Y10T428/12014 ,  Y10T428/24149 ,  Y10T428/249921 ,  Y10T428/25 ,  Y10T428/259 ,  H01L2924/00

摘要： Methods of forming insulating materials between conductive elements include forming a material adjacent a conductive electrical component comprising: partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. Other methods include forming a material between a pair of conductive electrical components comprising: forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components. Some embodiments include an insulating material adjacent a conductive electrical component, such material comprising a matrix and at least one void within the matrix.

摘要翻译： 在导电元件之间形成绝缘材料的方法包括形成邻近导电电气部件的材料，该材料包括：部分蒸发物质以形成邻近导电电气部件的基体，所述基体在其内具有至少一个空隙。 其他方法包括在一对导电电气部件之间形成材料，包括：在一个质量块内形成一对导电的电气部件，并由该质量块的一大片分隔; 在所述物体的宽度内形成至少一个支撑构件，所述支撑构件不包括导电互连; 以及使所述质量块的膨胀程度有效地在所述支撑构件和所述一对导电电气部件中的每一个之间形成至少一个空隙。 一些实施例包括邻近导电电气部件的绝缘材料，这种材料包括基质和基质内的至少一个空隙。

公开(公告)号：US06683003B2

公开(公告)日：2004-01-27

申请号：US09840496

申请日：2001-04-23

申请人： Guy Blalock

发明人： Guy Blalock

IPC分类号： H01L2100

CPC分类号： B29C43/56 ,  B29C43/32 ,  B29C2043/561 ,  B30B1/003 ,  B30B15/061 ,  H01L21/68742 ,  H01L21/68757 ,  H01L21/68785

摘要： An apparatus for performing a global planarization of a surface of a deformable layer of a wafer on a production scale. The apparatus includes a chamber having a pressing surface and containing a rigid plate and a flexible pressing member or “puck” disposed between the rigid plate and the pressing surface. A wafer having a deformable outermost layer is placed on the flexible pressing member so the deformable layer of the wafer is directly opposite and substantially parallel to the pressing surface. Force is applied to the rigid plate which propagates through the flexible pressing member to press the deformable layer of the wafer against the pressing surface. Preferably, a bellows arrangement is used to ensure a uniformly applied force to the rigid plate. The flexible puck serves to provide a self adjusting mode of uniformly distributing the applied force to the wafer, ensuring the formation of a high quality planar surface. The surface of the wafer assumes the shape of the pressing surface and is hardened in a suitable manner while under pressure to produce a globally planarized surface on the wafer. After the force is removed from the rigid plate, lift pins are slidably inserted through the rigid plate and the flexible pressing member to lift the wafer off of the surface of the flexible pressing member.

摘要翻译： 一种用于在生产规模上执行晶片的可变形层的表面的全局平坦化的装置。 该装置包括具有按压表面并容纳刚性板和设置在刚性板和按压表面之间的柔性按压构件或“圆盘”的腔室。 具有可变形最外层的晶片被放置在柔性按压构件上，使得晶片的可变形层直接相对并且基本上平行于按压表面。 将力施加到通过柔性按压构件传播的刚性板，以将晶片的可变形层压靠在按压表面上。 优选地，使用波纹管布置来确保对刚性板均匀施加的力。 柔性圆盘用于提供将施加的力均匀分布到晶片的自调节模式，确保形成高质量的平面表面。 晶片的表面呈压制表面的形状并且在压力下以合适的方式硬化以在晶片上产生全局平坦化的表面。 在从刚性板移除力之后，提升销可滑动地插入穿过刚性板和柔性按压构件以将晶片提离出柔性按压构件的表面。

公开(公告)号：US06429526B1

公开(公告)日：2002-08-06

申请号：US09310649

申请日：1999-05-12

申请人： Guy Blalock ,  Kirk Prall ,  Fernando Gonzalez

发明人： Guy Blalock ,  Kirk Prall ,  Fernando Gonzalez

IPC分类号： H01L2348

CPC分类号： H01L23/5283 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a connection is comprised of the steps of depositing a lower conductor. A dielectric layer is deposited on the lower conductor, with the dielectric layer having a lower surface adjacent to the lower conductor, and having an upper surface. An opening extending between the upper surface and the lower surface of the dielectric layer is formed. A conductive plug is deposited within the opening, with the plug having an upper surface proximate the upper surface of the dielectric layer. The upper surface has an edge where the upper surface of the plug is adjacent to the dielectric layer. A recess is formed proximate to the edge of the upper surface of the plug, the recess extending into both the plug and the dielectric layer. Finally, an upper conductor is deposited on the upper surface of the dielectric layer and the upper surface of the plug. A connection thus formed is also disclosed.

公开(公告)号：US06420786B1

公开(公告)日：2002-07-16

申请号：US08595806

申请日：1996-02-02

申请人： Fernando Gonzalez ,  Guy Blalock

发明人： Fernando Gonzalez ,  Guy Blalock

IPC分类号： H01L2348

CPC分类号： H01L21/76865 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of constructing a conductive via spacer within a dielectric layer located between a first metal layer and a second metal layer includes the steps of depositing a conductive spacer layer within the opening and over the first metal layer. A portion of the conductive spacer layer is removed to leave a conductive spacer within the opening. The second metal layer is deposited over the spacer to complete the connection between the first and second metal layers. The spacer preferably comprises a material selected from the group comprising refractory metal silicides and nitrides. The spacer is preferably tapered and the via may include a glue layer to improve the adherence of the spacer to the dielectric layer.

摘要翻译： 在位于第一金属层和第二金属层之间的电介质层内构造导电通孔间隔物的方法包括以下步骤：在开口内和第一金属层之上沉积导电隔离层。 去除导电间隔层的一部分以在开口内留下导电间隔物。 第二金属层沉积在间隔物上以完成第一和第二金属层之间的连接。 间隔物优选包含选自难熔金属硅化物和氮化物的材料。 间隔件优选是锥形的，并且通孔可以包括胶层，以改善间隔物对电介质层的粘附。

公开(公告)号：USRE37505E1

公开(公告)日：2002-01-15

申请号：US08628287

申请日：1996-04-05

申请人： Guy Blalock ,  Phillip G. Wald

发明人： Guy Blalock ,  Phillip G. Wald

IPC分类号： H01L2978

CPC分类号： H01L27/10852 ,  H01L27/10808 ,  H01L28/84 ,  H01L28/91 ,  Y10S438/964

摘要： A method of forming a capacitor on a semiconductor wafer includes: a) in a dry etching reactor, selectively anisotropically dry etching a capacitor contact opening having a minimum selected open dimension into an insulating dielectric layer utilizing selected gas flow rates of a reactive gas component and an inert gas bombarding component, the flow rate of the bombarding component significantly exceeding the flow rate of the reactive component to effectively produce a capacitor contact opening having grooved striated sidewalls and thereby defining female capacitor contact opening striations; b) providing a layer of an electrically conductive storage node material within the striated capacitor contact opening; c) removing at least a portion of the conductive material layer to define an isolated capacitor storage node within the insulating dielectric having striated sidewalls; d) etching the insulating dielectric layer selectively relative to the conductive material sufficiently to expose at least a portion of the external male striated conductive material sidewalls; and e) providing conformal layers of capacitor dielectric and capacitor cell material atop the etched conductive material and over its exposed striated sidewalls. The invention also includes a stacked capacitor construction having an electrically conductive storage node with upwardly rising external sidewalls. Such sidewalls have longitudinally extending striations to maximize surface area and corresponding capacitance in a resulting construction.

摘要翻译： 在半导体晶片上形成电容器的方法包括：a）在干式蚀刻反应器中，利用选择的反应性气体组分的气体流速，选择性地各向异性地将具有最小选定开口尺寸的电容器接触开口刻蚀成绝缘介电层;以及 惰性气体轰击组分，轰击组分的流速显着超过反应组分的流速，以有效地产生具有沟槽条纹侧壁的电容器接触开口，从而限定母电容器接触开口条纹; b）在条纹电容器接触开口内提供导电存储节点材料层; c）去除所述导电材料层的至少一部分以在所述绝缘电介质内限定具有条纹侧壁的隔离电容器存储节点; d）相对于导电材料选择性地蚀刻绝缘介电层，足以露出至少一部分外部凸纹状导电材料侧壁; 以及e）在蚀刻的导电材料的顶部和其暴露的条纹侧壁上提供电容器电介质和电容器电池材料的保形层。 本发明还包括具有具有向上升高的外侧壁的导电存储节点的堆叠电容器结构。 这样的侧壁具有纵向延伸的条纹，以在最终结构中最大化表面积和相应的电容。

公开(公告)号：US06333556B1

公开(公告)日：2001-12-25

申请号：US08947847

申请日：1997-10-09

申请人： Werner Juengling ,  Kirk D. Prall ,  Ravi Iyer ,  Gurtej S. Sandhu ,  Guy Blalock

发明人： Werner Juengling ,  Kirk D. Prall ,  Ravi Iyer ,  Gurtej S. Sandhu ,  Guy Blalock

IPC分类号： H01L23485

CPC分类号： H01L21/7682 ,  H01L21/02115 ,  H01L21/02118 ,  H01L21/02167 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  Y10T428/12014 ,  Y10T428/24149 ,  Y10T428/249921 ,  Y10T428/25 ,  Y10T428/259 ,  H01L2924/00

摘要： The invention encompasses methods of forming insulating materials between conductive elements. In one aspect, the invention includes a method of forming a material adjacent a conductive electrical component comprising: a) partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. In another aspect, the invention includes a method of forming a material between a pair of conductive electrical components comprising the following steps: a) forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; b) forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and c) vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components. In another aspect, the invention includes an insulating material adjacent a conductive electrical component, the insulating material comprising a matrix and at least one void within the matrix. In another aspect, the invention includes an insulating region between a pair of conductive electrical components comprising: a) a support member between the conductive electrical components, the support member not comprising a conductive interconnect; and b) at least one void between the support member and each of the pair of conductive electrical components.

摘要翻译： 本发明包括在导电元件之间形成绝缘材料的方法。 在一个方面，本发明包括形成邻近导电电气部件的材料的方法，该方法包括：a）部分蒸发物质以形成邻近导电电气部件的基体，所述基质在其内具有至少一个空隙。 另一方面，本发明包括一种在一对导电电气部件之间形成材料的方法，包括以下步骤：a）在质量体内形成一对导电的电气部件，并由质量块的一部分分隔; b）在所述物体的宽度内形成至少一个支撑构件，所述支撑构件不包括导电互连; 以及c）将所述物质的所述膨胀物蒸发至有效地在所述支撑构件和所述一对导电电气部件中的每一个之间形成至少一个空隙的程度。 在另一方面，本发明包括与导电电气部件相邻的绝缘材料，所述绝缘材料包含基体和所述基体内的至少一个空隙。 在另一方面，本发明包括在一对导电电气部件之间的绝缘区域，包括：a）导电电气部件之间的支撑部件，所述支撑部件不包括导电互连; 以及b）所述支撑构件和所述一对导电电气部件中的每一个之间的至少一个空隙。

公开(公告)号：US06313046B1

公开(公告)日：2001-11-06

申请号：US09115339

申请日：1998-07-14

申请人： Werner Juengling ,  Kirk D. Prall ,  Ravi Iyer ,  Gurtej S. Sandhu ,  Guy Blalock

发明人： Werner Juengling ,  Kirk D. Prall ,  Ravi Iyer ,  Gurtej S. Sandhu ,  Guy Blalock

IPC分类号： H01L2131

CPC分类号： H01L21/7682 ,  H01L21/02115 ,  H01L21/02118 ,  H01L21/02167 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  Y10T428/12014 ,  Y10T428/24149 ,  Y10T428/249921 ,  Y10T428/25 ,  Y10T428/259 ,  H01L2924/00

摘要： The invention encompasses methods of forming insulating materials between conductive elements. In one aspect, the invention includes a method of forming a material adjacent a conductive electrical component comprising: a) partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. In another aspect, the invention includes a method of forming a material between a pair of conductive electrical components comprising the following steps: a) forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; b) forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and c) vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components. In another aspect, the invention includes an insulating material adjacent a conductive electrical component, the insulating material comprising a matrix and at least one void within the matrix. In another aspect, the invention includes an insulating region between a pair of conductive electrical components comprising: a) a support member between the conductive electrical components, the support member not comprising a conductive interconnect; and b) at least one void between the support member and each of the pair of conductive electrical components.

摘要翻译： 本发明涵盖在导电元件之间形成绝缘材料的方法。 在一个方面，本发明包括形成邻近导电电气部件的材料的方法，该方法包括：a）部分蒸发物质以形成邻近导电电气部件的基体，所述基质在其内具有至少一个空隙。 另一方面，本发明包括一种在一对导电电气部件之间形成材料的方法，包括以下步骤：a）在质量体内形成一对导电的电气部件，并由质量块的一部分分隔; b）在所述物体的宽度内形成至少一个支撑构件，所述支撑构件不包括导电互连; 以及c）将所述物质的所述膨胀物蒸发至有效地在所述支撑构件和所述一对导电电气部件中的每一个之间形成至少一个空隙的程度。 在另一方面，本发明包括与导电电气部件相邻的绝缘材料，所述绝缘材料包含基体和所述基体内的至少一个空隙。 在另一方面，本发明包括在一对导电电气部件之间的绝缘区域，包括：a）导电电气部件之间的支撑部件，所述支撑部件不包括导电互连; 以及b）所述支撑构件和所述一对导电电气部件中的每一个之间的至少一个空隙。

公开(公告)号：US6066559A

公开(公告)日：2000-05-23

申请号：US985088

申请日：1997-12-04

申请人： Fernando Gonzalez ,  Guy Blalock ,  Kirk Prall

发明人： Fernando Gonzalez ,  Guy Blalock ,  Kirk Prall

IPC分类号： H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L21/44

CPC分类号： H01L23/5283 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/535 ,  H01L2924/0002

摘要： A method of forming a connection is comprised of the steps of depositing a lower conductor. A dielectric layer is deposited on the lower conductor, with the dielectric layer having a lower surface adjacent to the lower conductor, and having an upper surface. An opening extending between the upper surface and the lower surface of the dielectric layer is formed. A conductive plug is deposited within the opening, with the plug having an upper surface proximate the upper surface of the dielectric layer. The upper surface has an edge where the upper surface of the plug is adjacent to the dielectric layer. A recess is formed proximate to the edge of the upper surface of the plug, the recess extending into both the plug and the dielectric layer. Finally, an upper conductor is deposited on the upper surface of the dielectric layer and the upper surface of the plug. A connection thus formed is also disclosed.

公开(公告)号：US5783100A

公开(公告)日：1998-07-21

申请号：US752064

申请日：1996-11-19

申请人： Guy Blalock ,  Kevin Donohoe

发明人： Guy Blalock ,  Kevin Donohoe

IPC分类号： H01L21/02

CPC分类号： H01L21/02

摘要： An improved method of high density plasma etching for etching substrates such as semiconductor wafers is provided. The method includes controlling the ratio of ions to neutrals in a high density plasma using an ion filter located in the flow path of the plasma. The ion filter is adapted to interrupt and deflect ions in the plasma while allowing neutrals to pass through to the substrate unaffected. This helps to prevent notching because a more favorable ion/neutral ratio is present at the substrate. At the same time etch selectivity is high, particularly for etching polysilicon to oxide, because current density can remain high.

摘要翻译： 提供了用于蚀刻诸如半导体晶片的基板的高密度等离子体蚀刻的改进方法。 该方法包括使用位于等离子体的流动路径中的离子过滤器来控制高密度等离子体中的离子与中性粒子的比例。 离子过滤器适于中断和偏转等离子体中的离子，同时允许中性粒子不受影响地通过衬底。 这有助于防止开槽，因为在衬底上存在更有利的离子/中性比。 同时，蚀刻选择性高，特别是对于蚀刻多晶硅至氧化物，因为电流密度可以保持高。