公开(公告)号：US12080778B2

公开(公告)日：2024-09-03

申请号：US18238534

申请日：2023-08-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： An-Chi Liu ,  Chun-Hsien Lin

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/201 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/404 ,  H01L29/778

Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, a barrier layer on the buffer layer, a gate electrode on the barrier layer, a field plate adjacent to two sides of the gate electrode, and a first passivation layer adjacent to two sides of the gate electrode. Preferably, a sidewall of the field plate includes a first curve.

公开(公告)号：US20240204085A1

公开(公告)日：2024-06-20

申请号：US18105798

申请日：2023-02-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Yang ,  Ssu-I Fu ,  Chih-Kai Hsu ,  Chun-Hsien Lin

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/02293 ,  H01L29/42312 ,  H01L29/785

Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate having a high-voltage (HV) region and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first gate structure on the substrate and a first epitaxial layer adjacent to the first gate structure, in which a top surface of the first epitaxial layer includes a first V-shape. The LV device includes a second gate structure on the substrate and a second epitaxial layer adjacent to the second gate structure, in which a top surface of the second epitaxial layer includes a first planar surface.

公开(公告)号：US11758824B2

公开(公告)日：2023-09-12

申请号：US17209251

申请日：2021-03-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： An-Chi Liu ,  Chun-Hsien Lin

IPC: H10N50/80 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

CPC classification number: H10N50/80 ,  G11C11/161 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, an inter-metal dielectric (IMD) layer on the substrate, a MTJ in the IMD layer on the MTJ region, a first metal interconnection in the IMD layer on the logic region, and protrusions adjacent to two sides of the first metal interconnection. Preferably, the MTJ further includes a bottom electrode, a fixed layer, a barrier layer, a free layer, and a top electrode.

公开(公告)号：US11735646B2

公开(公告)日：2023-08-22

申请号：US17090902

申请日：2020-11-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Chang Lin ,  Bo-Han Huang ,  Chih-Chung Chen ,  Chun-Hsien Lin ,  Shih-Hung Tsai ,  Po-Kuang Hsieh

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L29/66795 ,  H01L21/02052 ,  H01L21/02054 ,  H01L29/517 ,  H01L29/7851

Abstract: A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50° C. to 100° C., and a duration of the baking process is between 5 seconds to 120 seconds.

公开(公告)号：US20230090612A1

公开(公告)日：2023-03-23

申请号：US17991765

申请日：2022-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chun-Hsien Lin ,  Chien-Hung Chen

IPC: H01L27/11 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L21/8238 ,  H01L21/285 ,  H01L29/45

Abstract: A method for fabricating a static random access memory (SRAM) includes the steps of: forming a gate structure on a substrate; forming an epitaxial layer adjacent to the gate structure; forming a first interlayer dielectric (ILD) layer around the gate structure; transforming the gate structure into a metal gate; forming a contact hole exposing the epitaxial layer, forming a barrier layer in the contact hole, forming a metal layer on the barrier layer, and then planarizing the metal layer and the barrier layer to form a contact plug. Preferably, a bottom portion of the barrier layer includes a titanium rich portion and a top portion of the barrier layer includes a nitrogen rich portion.

公开(公告)号：US20230009805A1

公开(公告)日：2023-01-12

申请号：US17393384

申请日：2021-08-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Hung Tsai ,  Hon-Huei Liu ,  Chun-Hsien Lin

IPC: H03H9/05 ,  H03H3/08 ,  H03H9/02

Abstract: A method for fabricating a surface acoustic wave (SAW) device includes the steps of forming a first dielectric layer on a substrate, forming a piezoelectric layer on the first dielectric layer, forming a second dielectric layer on the piezoelectric layer, performing a photo-etching process to remove the second dielectric layer for forming a recess in the second dielectric layer, forming a metal layer in the recess, and then performing a planarizing process to remove the metal layer for forming an electrode in the recess.

公开(公告)号：US11552181B2

公开(公告)日：2023-01-10

申请号：US17088522

申请日：2020-11-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Lin

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3213

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a fin-shaped structure on a substrate, forming a gate material layer on the fin-shaped structure, performing an etching process to pattern the gate material layer for forming a gate structure and a silicon residue, performing an ashing process on the silicon residue, and then performing a cleaning process to transform the silicon residue into a polymer stop layer on a top surface and sidewalls of the fin-shaped structure.

公开(公告)号：US11367725B2

公开(公告)日：2022-06-21

申请号：US17079537

申请日：2020-10-26

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Chun-Hsien Lin ,  Fu-Che Lee

IPC: H01L27/108 ,  H01L29/423 ,  H01L21/02 ,  H01L29/49 ,  H01L29/51 ,  H01L29/06

Abstract: A method for fabricating a buried word line (BWL) of a dynamic random access memory (DRAM) includes the steps of: forming a first doped region in a substrate; removing part of the first doped region to form a trench in the substrate; forming a gate structure in the trench; and forming a barrier structure between the gate structure and the first doped region.

公开(公告)号：US20220173306A1

公开(公告)日：2022-06-02

申请号：US17134485

申请日：2020-12-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chun-Hsien Lin

IPC: H01L43/02 ,  H01L27/22

Abstract: A semiconductor device for internet of things (IoT) device includes a substrate having an array region defined thereon and a ring of dummy pattern surrounding the array region. Preferably, the ring of dummy pattern includes a plurality of magnetic tunneling junctions (MTJs) and a ring of metal interconnect pattern overlapping the MTJs and surrounding the array region. The semiconductor device further includes a gap between the array region and the ring of dummy pattern.

公开(公告)号：US20220013715A1

公开(公告)日：2022-01-13

申请号：US16985206

申请日：2020-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Wei Liu ,  Jia-Feng Fang ,  Chun-Hsien Lin

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02

Abstract: A method for fabricating semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) stack on a substrate, performing an etching process to remove the MTJ stack for forming a MTJ, performing a deposition process to form a polymer on a sidewall of the MTJ, and removing the polymer to form a rough surface on the sidewall of the MTJ. Preferably, the MTJ could include a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer, in which the rough surface could appear on sidewall of the pinned layer, sidewall of the barrier layer, and/or sidewall of the free layer.