公开(公告)号：US20110221064A1

公开(公告)日：2011-09-15

申请号：US13114342

申请日：2011-05-24

申请人： Jonathan D. Chapple-Sokol ,  Daniel A. Delibac ,  Zhong-Xiang He ,  Tom C. Lee ,  William J. Murphy ,  Timothy D. Sullivan ,  David C. Thomas ,  Daniel S. Vanslette

发明人： Jonathan D. Chapple-Sokol ,  Daniel A. Delibac ,  Zhong-Xiang He ,  Tom C. Lee ,  William J. Murphy ,  Timothy D. Sullivan ,  David C. Thomas ,  Daniel S. Vanslette

IPC分类号： H01L23/522

CPC分类号： H01L21/76834 ,  H01L21/32051 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76858 ,  H01L2221/1078

摘要： A vertical metallic stack, from bottom to top, of an elemental metal liner, a metal nitride liner, a Ti liner, an aluminum portion, and a metal nitride cap, is formed on an underlying metal interconnect structure. The vertical metallic stack is annealed at an elevated temperature to induce formation of a TiAl3 liner by reaction of the Ti liner with the material of the aluminum portion. The material of the TiAl3 liner is resistant to electromigration, thereby providing enhanced electromigration resistance to the vertical metallic stack comprising the elemental metal liner, the metal nitride liner, the TiAl3 liner, the aluminum portion, and the metal nitride cap. The effect of enhanced electromigration resistance may be more prominent in areas in which the metal nitride cap suffers from erosion during processing.

摘要翻译： 在下面的金属互连结构上形成由元素金属衬垫，金属氮化物衬垫，Ti衬垫，铝部分和金属氮化物盖的从底部到顶部的垂直金属堆叠。 垂直金属叠层在升高的温度下退火，以通过Ti衬垫与铝部分的材料反应而引起TiAl 3衬层的形成。 TiAl 3衬垫的材料对电迁移是耐受的，从而对包括元素金属衬垫，金属氮化物衬垫，TiAl 3衬里，铝部分和金属氮化物盖的垂直金属堆叠提供增强的电迁移阻力。 在金属氮化物盖在加工过程中遭受侵蚀的区域中，增强的耐电迁移性的作用可能更为突出。

公开(公告)号：US07956671B2

公开(公告)日：2011-06-07

申请号：US12496002

申请日：2009-07-01

申请人： Michel J. Abou-Khalil ,  Tom C. Lee ,  Junjun Li ,  Robert J. Gauthier, Jr. ,  Christopher S. Putnam ,  Souvick Mitra

发明人： Michel J. Abou-Khalil ,  Tom C. Lee ,  Junjun Li ,  Robert J. Gauthier, Jr. ,  Christopher S. Putnam ,  Souvick Mitra

IPC分类号： H01L23/52

CPC分类号： G11C17/16 ,  G11C11/5692 ,  H01L23/5252 ,  H01L23/5256 ,  H01L27/101 ,  H01L27/112 ,  H01L27/11206 ,  H01L45/085 ,  H01L45/1206 ,  H01L45/14 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment of an e-fuse programming/re-programming circuit, the e-fuse has two short high atomic diffusion resistance conductor layers positioned on opposite sides and at a same end of a long low atomic diffusion resistance conductor layer. A voltage source is used to vary the polarity and, optionally, the magnitude of voltage applied to the terminals in order to control bi-directional flow of electrons within the long conductor layer and, thereby formation of opens and/or shorts at the long conductor layer-short conductor layer interfaces. The formation of such opens and/or shorts can be used to achieve different programming states. Other circuit structure embodiments incorporate e-fuses with additional conductor layers and additional terminals so as to allow for even more programming states. Also disclosed are embodiments of associated e-fuse programming and re-programming methods.

摘要翻译： 在电熔丝编程/重新编程电路的一个实施例中，电熔丝具有位于长低的原子扩散电阻较长的导体层的相对侧和同一端的两个短的高原子扩散电阻的导体层。 电压源用于改变施加到端子的电压的极性和可选的电压大小，以便控制长导体层内电子的双向流动，从而在长导体上形成开路和/或短路 层 - 短导体层接口。 可以使用这种打开和/或短路的形成来实现不同的编程状态。 其他电路结构实施例包括具有附加导体层和附加端子的电子保险丝，以便允许甚至更多的编程状态。 还公开了相关联的电熔丝编程和重新编程方法的实施例。

公开(公告)号：US20090256202A1

公开(公告)日：2009-10-15

申请号：US12102032

申请日：2008-04-14

申请人： Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Christopher S. Putnam ,  Souvick Mitra

发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Christopher S. Putnam ,  Souvick Mitra

IPC分类号： H01L29/786

CPC分类号： H01L27/1203 ,  H01L27/0248

摘要： Semiconductor-on-insulator device structures with enhanced electrostatic discharge protection, and design structures for an integrated circuit with device structures exhibiting enhanced electrostatic discharge protection. A device is formed in a body region of a device layer of a semiconductor-on-insulator substrate, which is bounded by an inner peripheral sidewall of an annular dielectric-filled isolation structure that extends from a top surface of the device layer to the insulating layer of the semiconductor-on-insulator substrate. An annular conductive interconnect extends through the body region and the insulating layer to connect the body region with the bulk wafer of the semiconductor-on-insulator substrate. The annular conductive interconnect is disposed inside the inner peripheral sidewall of the isolation structure, which annularly encircles the body region.

摘要翻译： 具有增强的静电放电保护的绝缘体上半导体器件结构以及具有增强的静电放电保护的器件结构的集成电路的设计结构。 一种器件形成在绝缘体上半导体衬底的器件层的体区中，该衬底由环形电介质填充的隔离结构的内周侧壁限定，该隔离结构从器件层的顶表面延伸到绝缘体 绝缘体上半导体衬底的层。 环形导电互连延伸穿过主体区域和绝缘层，以将体区域与绝缘体上半导体衬底的体晶片连接。 环形导电互连件设置在隔离结构的内周侧壁的内侧，环形环绕主体区域。

公开(公告)号：US20090179689A1

公开(公告)日：2009-07-16

申请号：US11971937

申请日：2008-01-10

申请人： Ronald J. Bolam ,  Tom C. Lee ,  Timothy D. Sullivan

发明人： Ronald J. Bolam ,  Tom C. Lee ,  Timothy D. Sullivan

IPC分类号： H03K3/42 ,  H01L21/00

CPC分类号： H01L23/345 ,  H01L22/14 ,  H01L22/20 ,  H01L23/5228 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed are embodiments of a semiconductor chip structure and a method that incorporate a localized, on-chip, repair scheme for devices that exhibit performance degradation as a result of negative bias temperature instability (NBTI). The repair scheme utilizes a heating element above each device. The heating element is configured so that it can receive transmission line pulses and, thereby generate enough heat to raise the adjacent device to a temperature sufficient to allow for performance recovery. Specifically, high temperatures (e.g., between approximately 300-400° C. or greater) in the absence of bias can accelerate the recovery process to a matter of seconds as opposed to days or months. The heating element can be activated, for example, on demand, according to a pre-set service schedule, and/or in response to feedback from a device performance monitor.

摘要翻译： 公开了半导体芯片结构的实施例和一种对于由于负偏压温度不稳定性（NBTI）而表现出性能劣化的器件而并入局部的片上修复方案的方法。 修理方案在每个设备上使用加热元件。 加热元件被配置成使得其可以接收传输线脉冲，并且由此产生足够的热量以将相邻设备升高到足以允许性能恢复的温度。 具体而言，在不存在偏压的情况下，高温（例如，约300-400℃或更高）可以将恢复过程加速到几秒钟，而不是几天或几个月。 加热元件例如可以根据预先设定的服务时间表和/或响应于来自设备性能监视器的反馈而被激活。

公开(公告)号：US20090160013A1

公开(公告)日：2009-06-25

申请号：US11960030

申请日：2007-12-19

申请人： Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

IPC分类号： H01L29/00 ,  H01L21/4763

CPC分类号： H01L23/34 ,  H01L21/743 ,  H01L21/76877 ,  H01L21/84 ,  H01L23/3677 ,  H01L27/0255 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A heat generating component of a semiconductor device is located between two heavily doped semiconductor regions in a semiconductor substrate. The heat generating component may be a middle portion of a diode having a light doping, a lightly doped p-n junction between a cathode and anode of a silicon controlled rectifier, or a resistive portion of a doped semiconductor resistor. At least one thermally conductive via comprising a metal or a non-metallic conductive material is place directly on the heat generating component. Alternatively, a thin dielectric layer may be formed between the heat generating component and the at least one thermally conductive via. The at least one thermally conductive via may, or may not, be connected to a back-end-of-line metal wire, which may be connected to higher level of metal wiring or to a handle substrate through a buried insulator layer.

摘要翻译： 半导体器件的发热元件位于半导体衬底中的两个重掺杂半导体区之间。 发热部件可以是具有轻掺杂的二极管的中间部分，可控硅整流器的阴极和阳极之间的轻掺杂p-n结或掺杂半导体电阻器的电阻部分。 至少一个包含金属或非金属导电材料的导热通孔直接放置在发热部件上。 或者，可以在发热部件和至少一个导热通孔之间形成薄介电层。 至少一个导热通孔可以连接到或可以不连接到后端金属线，其可以通过掩埋绝缘体层连接到较高级别的金属布线或者与手柄基板连接。

公开(公告)号：US07397260B2

公开(公告)日：2008-07-08

申请号：US11163948

申请日：2005-11-04

申请人： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Ronald G. Filippi ,  Jason P. Gill ,  Tom C. Lee ,  Baozhen Li ,  Paul S. McLaughlin ,  Du B. Nguyen ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Chih-Chao Yang

发明人： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Ronald G. Filippi ,  Jason P. Gill ,  Tom C. Lee ,  Baozhen Li ,  Paul S. McLaughlin ,  Du B. Nguyen ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Chih-Chao Yang

IPC分类号： G01R31/02 ,  H01L23/58 ,  G01N25/20

CPC分类号： G01R31/2858 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (μm).

摘要翻译： 提供了诸如芯片或微电子布线基板的微电子元件，其包括用于改善耐热应力的多个导电互连。 至少一些导电互连件包括金属板，金属连接线和上金属通孔。 所述金属连接线具有与所述金属板的上表面至少基本平齐的上表面，在所述周边边缘中的一个处连接到所述金属板的内端和从所述一个周边边缘水平移位的外端。 金属连接线的宽度远小于金属板的一个周边边缘的宽度，并且其长度大于一个周边边缘的宽度。 上金属通孔在与一个外围边缘水平位移至少约3微米（mum）的位置处具有与金属连接线接触的底端。

公开(公告)号：US07384824B2

公开(公告)日：2008-06-10

申请号：US11362680

申请日：2006-02-27

申请人： Dinesh A. Badami ,  Tom C. Lee ,  Baozhen Li ,  Gerald Matusiewicz ,  William T. Motsiff ,  Christopher D. Muzzy ,  Kimball M. Watson ,  Jean E. Wynne

发明人： Dinesh A. Badami ,  Tom C. Lee ,  Baozhen Li ,  Gerald Matusiewicz ,  William T. Motsiff ,  Christopher D. Muzzy ,  Kimball M. Watson ,  Jean E. Wynne

IPC分类号： H01L21/82 ,  H01L29/00

CPC分类号： H01L23/5258 ,  H01L23/525 ,  H01L23/5254 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for fabricating a laser fuse and a method for programming the laser fuse. The laser fuse includes a dielectric layer having two vias filled with a first self-passivated electrically conducting material. A fuse link is on top of the dielectric layer. The fuse link electrically connects the two vias and includes a second material having a characteristic of changing its electrical resistance after being exposed to a laser beam. Two mesas are over the fuse link and directly over the two vias. The two mesas each include a third self-passivated electrically conducting material. The laser fuse is programmed by directing a laser beam to the fuse link. The laser beam is controlled such that, in response to the impact of the laser beam upon the fuse link, the electrical resistance of the fuse link changes but the fuse link is not blown off. Such electrical resistance change is sensed and converted to digital signal.

摘要翻译： 用于制造激光熔丝的方法和结构以及用于编程激光熔丝的方法。 激光熔丝包括具有填充有第一自钝化导电材料的两个通孔的电介质层。 熔丝连接在电介质层的顶部。 熔断体将两个通孔电连接并且包括具有在暴露于激光束之后改变其电阻的特性的第二材料。 两个台面位于熔丝链上方，直接穿过两个通孔。 两个台面各自包括第三自钝化导电材料。 激光熔丝通过将激光束引导到熔丝链来编程。 控制激光束，使得响应于激光束对熔丝链的影响，熔丝链的电阻改变，但熔丝链不会被吹掉。 这种电阻变化被检测并转换成数字信号。