公开(公告)号：US08503240B2

公开(公告)日：2013-08-06

申请号：US13550157

申请日：2012-07-16

申请人： Kevin M. Conley ,  John S. Mangan ,  Jeffrey G. Craig

发明人： Kevin M. Conley ,  John S. Mangan ,  Jeffrey G. Craig

IPC分类号： G11C16/04

CPC分类号： G11C16/107 ,  G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7207 ,  G06F2212/7208 ,  G11C16/10 ,  G11C16/3459 ,  G11C29/82 ,  G11C2216/14

摘要： A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system. The memory cells may be operated with multiple states in order to store more than one bit of data per cell.

摘要翻译： 非易失性存储器系统由以块为单位布置的浮动栅极存储单元形成为可以一起可擦除的最小单元的存储器单元。 一个特征是在单独的块中存储其中存储用户数据的大量小区块的特性。 正在访问的用户数据块的这些特征可以在存储器系统由其控制器操作期间被存储在随机存取存储器中以便于访问和更新。 存储器系统的典型形式是可拆卸地与主机系统连接的卡，但是也可以在嵌入在主机系统中的存储器中实现。 存储器单元可以以多种状态操作，以便存储每个单元的多于一位的数据。

公开(公告)号：US08301826B2

公开(公告)日：2012-10-30

申请号：US12609789

申请日：2009-10-30

申请人： Carlos J. Gonzalez ,  Mark Sompel ,  Kevin M. Conley

发明人： Carlos J. Gonzalez ,  Mark Sompel ,  Kevin M. Conley

IPC分类号： G06F12/00

CPC分类号： G06F12/0607 ,  G06F12/0246 ,  G06F2212/7202 ,  G06F2212/7208

摘要： In a non-volatile memory storage system such as a flash EEPROM system, a controller switches the manner in which data sectors are mapped into blocks and metablocks of the memory in response to host programming and controller data consolidation patterns, in order to improve performance and reduce wear. Data are programmed into the memory with different degrees of parallelism.

摘要翻译： 在诸如闪存EEPROM系统的非易失性存储器系统中，响应于主机编程和控制器数据合并模式，控制器将数据扇区映射到存储器的块和元区块的方式切换，以便提高性能和 减少磨损。 数据被编程到具有不同程度的并行性的存储器中。

公开(公告)号：US20120092795A1

公开(公告)日：2012-04-19

申请号：US12904006

申请日：2010-10-13

申请人： Donald A. LIEBERMAN ,  Michael O'Connor ,  Raymond Bruce Wong ,  Kevin M. Conley

发明人： Donald A. LIEBERMAN ,  Michael O'Connor ,  Raymond Bruce Wong ,  Kevin M. Conley

IPC分类号： H02H9/02

CPC分类号： H02J13/0003 ,  G06F1/26 ,  G06F1/30 ,  Y02B90/228 ,  Y04S20/18

摘要： A method and apparatus for managing over current protection in a power supply unit is disclosed. One aspect of certain embodiments includes comparing for each conductor of a plurality of conductors the current flowing through the particular conductor with over current protection limit associated with that particular conductor.

摘要翻译： 公开了一种用于管理电源单元中的过电流保护的方法和装置。 某些实施例的一个方面包括比较多个导体的每个导体，流过特定导体的电流与该特定导体相关联的过电流保护极限。

公开(公告)号：US08117380B2

公开(公告)日：2012-02-14

申请号：US12433702

申请日：2009-04-30

申请人： Kevin M. Conley ,  Carlos J. Gonzalez

发明人： Kevin M. Conley ,  Carlos J. Gonzalez

IPC分类号： G06F12/02 ,  G06F13/00

CPC分类号： G06F12/0246 ,  G06F2212/7202

摘要： A non-volatile memory system of a type having blocks of memory cells erased together and which are programmable from an erased state in units of a large number of pages per block. If the data of only a few pages of a block are to be updated, the updated pages are written into another block provided for this purpose. The valid original and updated data are then combined at a later time, when doing so does not impact on the performance of the memory. If the data of a large number of pages of a block are to be updated, however, the updated pages are written into an unused erased block and the unchanged pages are also written to the same unused block. By handling the updating of a few pages differently, memory performance is improved when small updates are being made.

摘要翻译： 一种类型的非易失性存储器系统，其具有一起擦除的存储器单元的块，并且可以以每块的大量页面为单位从擦除状态编程。 如果要更新块的几页数据，则更新的页面被写入为此目的提供的另一个块。 然后，有效的原始和更新的数据在稍后的时间被组合，当这样做不影响存储器的性能时。 然而，如果要更新块的大量页面的数据，则更新的页面被写入未使用的擦除块，并且未改变的页面也被写入到相同的未使用的块。 通过不同的处理几页的更新，当进行小型更新时，内存性能得到改善。

公开(公告)号：US20110258386A1

公开(公告)日：2011-10-20

申请号：US13168756

申请日：2011-06-24

申请人： Kevin M. Conley

发明人： Kevin M. Conley

IPC分类号： G06F12/00

CPC分类号： G11C16/102 ,  G06F12/0246 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/7202 ,  G06F2212/7208 ,  G06F2212/7209 ,  G11C16/105 ,  G11C2216/16

摘要： Data in less than all of the pages of a non-volatile memory block are updated by programming the new data in unused pages of either the same or another block. In order to prevent having to copy unchanged pages of data into the new block, or to program flags into superceded pages of data, the pages of new data are identified by the same logical address as the pages of data which they superceded and a time stamp is added to note when each page was written. When reading the data, the most recent pages of data are used and the older superceded pages of data are ignored. This technique is also applied to metablocks that include one block from each of several different units of a memory array, by directing all page updates to a single unused block in one of the units.

公开(公告)号：US08004895B2

公开(公告)日：2011-08-23

申请号：US12415158

申请日：2009-03-31

申请人： Carlos J. Gonzalez ,  Kevin M. Conley

发明人： Carlos J. Gonzalez ,  Kevin M. Conley

IPC分类号： G11C16/04

CPC分类号： G06F11/106 ,  G06F11/1068 ,  G11C8/08

摘要： In order to maintain the integrity of data stored in a flash memory that are susceptible to being disturbed by operations in adjacent regions of the memory, disturb events cause the data to be read, corrected and re-written before becoming so corrupted that valid data cannot be recovered. The sometimes conflicting needs to maintain data integrity and system performance are balanced by deferring execution of some of the corrective action when the memory system has other high priority operations to perform. In a memory system utilizing very large units of erase, the corrective process is executed in a manner that is consistent with efficiently rewriting an amount of data much less than the capacity of a unit of erase.

公开(公告)号：US20110134696A1

公开(公告)日：2011-06-09

申请号：US13027055

申请日：2011-02-14

申请人： Kevin M. Conley ,  John S. Mangan ,  Jeffrey G. Craig

发明人： Kevin M. Conley ,  John S. Mangan ,  Jeffrey G. Craig

IPC分类号： G11C16/04

CPC分类号： G11C16/107 ,  G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7207 ,  G06F2212/7208 ,  G11C16/10 ,  G11C16/3459 ,  G11C29/82 ,  G11C2216/14

摘要： A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data. The stream of data may further be transformed in order to tend to even out the wear among the blocks of memory. Yet another feature, for memory systems having multiple memory integrated circuit chips, provides a single system record that includes the capacity of each of the chips and assigned contiguous logical address ranges of user data blocks within the chips which the memory controller accesses when addressing a block, making it easier to manufacture a memory system with memory chips having different capacities. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system. The memory cells may be operated with multiple states in order to store more than one bit of data per cell.

摘要翻译： 非易失性存储器系统由以块为单位布置的浮动栅极存储单元形成为可以一起可擦除的最小单元的存储器单元。 该系统包括可以单独地或以各种协作组合实现的多个特征。 一个特征是在单独的块中存储其中存储用户数据的大量小区块的特性。 正在访问的用户数据块的这些特征可以在存储器系统由其控制器操作期间被存储在随机存取存储器中以便于访问和更新。 根据另一特征，通过将来自扇区的数据块交替地流向多个存储块，一次存储多个扇区的用户数据。 可以移动流中的数据字节以避免存储器中的不良位置，例如不良列。 也可以通过用于多扇区数据的单一生成电路从流数据生成纠错码。 可以进一步转换数据流，以便趋向于均匀地消除存储器块之间的磨损。 对于具有多个存储器集成电路芯片的存储器系统，又一特征提供了单个系统记录，该系统记录包括每个芯片的容量，并且在寻址块时存储器控制器访问的芯片内分配的用户数据块的连续逻辑地址范围 ，使得容易制造具有不同容量的存储器芯片的存储器系统。 存储器系统的典型形式是可拆卸地与主机系统连接的卡，但是也可以在嵌入在主机系统中的存储器中实现。 存储器单元可以以多种状态操作，以便存储每个单元的多于一位的数据。

公开(公告)号：US20110029724A1

公开(公告)日：2011-02-03

申请号：US12900397

申请日：2010-10-07

申请人： Kevin M. Conley

发明人： Kevin M. Conley

IPC分类号： G06F12/02 ,  G06F12/00

CPC分类号： G11C16/102 ,  G06F12/0246 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/7202 ,  G06F2212/7208 ,  G06F2212/7209 ,  G11C16/105 ,  G11C2216/16

摘要： Data in less than all of the pages of a non-volatile memory block are updated by programming the new data in unused pages of either the same or another block. In order to prevent having to copy unchanged pages of data into the new block, or to program flags into superceded pages of data, the pages of new data are identified by the same logical address as the pages of data which they superceded and a time stamp is added to note when each page was written. When reading the data, the most recent pages of data are used and the older superceded pages of data are ignored. This technique is also applied to metablocks that include one block from each of several different units of a memory array, by directing all page updates to a single unused block in one of the units.

摘要翻译： 通过对相同或另一块的未使用页面中的新数据进行编程来更新少于非易失性存储器块的所有页面中的数据。 为了防止不必要将不变的数据页复制到新的块中，或者将标记编程到被替换的数据页面中，新数据的页面被与它们所取代的数据页面相同的逻辑地址标识，并且时间戳 当每个页面被写入时都会添加注释。 当读取数据时，将使用最新的数据页面，并忽略较旧的旧版数据页面。 通过将所有页面更新指向一个单元中的单个未使用的块，该技术也应用于包含来自存储器阵列的几个不同单元中的每一个的一个块的元区块。

公开(公告)号：US07778077B2

公开(公告)日：2010-08-17

申请号：US11383397

申请日：2006-05-15

申请人： Sergey Anatolievich Gorobets ,  Kevin M. Conley

发明人： Sergey Anatolievich Gorobets ,  Kevin M. Conley

IPC分类号： G11C11/34

CPC分类号： G11C8/10 ,  G11C16/349 ,  G11C16/3495

摘要： A system and methods are given for providing information on the amount of life remaining for a memory having a limited lifespan, such as a flash memory card. For example, it can provide a user with the amount of the memory's expected remaining lifetime in real time units (i.e., hours or days) or as a percentage of estimated initial life. An end of life warning can also be provided. In a particular embodiment, the amount of remaining life (either as a percentage or in real time units) can be based on the average number of erases per block, but augmented by the number of spare blocks or other parameters, so that an end of life warning is given if either the expected amount of remaining life falls below a certain level or the number of spare blocks falls below a safe level.

摘要翻译： 给出了提供关于具有有限寿命的存储器（例如闪存卡）的剩余寿命的信息的系统和方法。 例如，它可以向用户提供实时单位（即，小时或天）中的存储器的预期剩余寿命的量，或作为估计的初始寿命的百分比。 也可以提供生命警告的结束。 在特定实施例中，剩余寿命的量（以百分比或实时单位计）可以基于每个块的平均擦除次数，但是增加了备用块的数量或其他参数，使得结束 如果预期的剩余生命量低于一定水平或备用块数量低于安全水平，则会发出生命警告。

公开(公告)号：US20100067298A1

公开(公告)日：2010-03-18

申请号：US12624258

申请日：2009-11-23

申请人： Kevin M. Conley ,  John S. Mangan ,  Jeffrey G. Craig

发明人： Kevin M. Conley ,  John S. Mangan ,  Jeffrey G. Craig

IPC分类号： G11C16/04 ,  G11C16/10

CPC分类号： G11C16/107 ,  G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7207 ,  G06F2212/7208 ,  G11C16/10 ,  G11C16/3459 ,  G11C29/82 ,  G11C2216/14

摘要： A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data. The stream of data may further be transformed in order to tend to even out the wear among the blocks of memory. Yet another feature, for memory systems having multiple memory integrated circuit chips, provides a single system record that includes the capacity of each of the chips and assigned contiguous logical address ranges of user data blocks within the chips which the memory controller accesses when addressing a block, making it easier to manufacture a memory system with memory chips having different capacities. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system. The memory cells may be operated with multiple states in order to store more than one bit of data per cell.

摘要翻译： 非易失性存储器系统由以块为单位布置的浮动栅极存储单元形成为可以一起可擦除的最小单元的存储器单元。 该系统包括可以单独地或以各种协作组合实现的多个特征。 一个特征是在单独的块中存储其中存储用户数据的大量小区块的特性。 正在访问的用户数据块的这些特征可以在存储器系统由其控制器操作期间被存储在随机存取存储器中以便于访问和更新。 根据另一特征，通过将来自扇区的数据块交替地流向多个存储块，一次存储多个扇区的用户数据。 可以移动流中的数据字节以避免存储器中的不良位置，例如不良列。 也可以通过用于多扇区数据的单一生成电路从流数据生成纠错码。 可以进一步转换数据流，以便趋向于均匀地消除存储器块之间的磨损。 对于具有多个存储器集成电路芯片的存储器系统，又一特征提供了单个系统记录，该系统记录包括每个芯片的容量，并且在寻址块时存储器控制器访问的芯片内分配的用户数据块的连续逻辑地址范围 ，使得容易制造具有不同容量的存储器芯片的存储器系统。 存储器系统的典型形式是可拆卸地与主机系统连接的卡，但是也可以在嵌入在主机系统中的存储器中实现。 存储器单元可以以多种状态操作，以便存储每个单元的多于一位的数据。