公开(公告)号：US20060163612A1

公开(公告)日：2006-07-27

申请号：US10559979

申请日：2004-06-14

申请人： John Kouvetakis ,  Matthew Bauer

发明人： John Kouvetakis ,  Matthew Bauer

IPC分类号： H01L29/739

CPC分类号： H01L31/028 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/0259 ,  H01L21/0262 ,  H01L29/161 ,  H01L29/165 ,  Y02E10/547 ,  Y10S148/169 ,  Y10S438/936

摘要： A novel method for synthesizing device-quality alloys and ordered phases in a Si—Ge—Sn system uses a UHV-CVD process and reactions of SnD4 with SiH3GeH3. Using the method, single-phase SixSnyGe1-x-y semiconductors (x≦0.25, y≦0.11) are grown on Si via Ge1-xSnx buffer layers The Ge1-xSnx buffer layers facilitate heteroepitaxial growth of the SixSnyGe1-x-y, films and act as compliant templates that can conform structurally and absorb the differential strain imposed by the more rigid Si and Si—Ge—Sn materials. The SiH3GeH3 species was prepared using a new and high yield method that provided high purity semiconductor grade material.

摘要翻译： 在Si-Ge-Sn系统中合成器件质量合金和有序相的新方法使用UHV-CVD工艺，并且SnD <4> 与SiH 3 GeH SUB> 3 。 使用该方法，生长单相Si x 1 Sn y y Ge 1-xy x半导体（x <= 0.25，y <= 0.11） 在Si上通过Ge 1-x Sn Sn x缓冲层。Ge 1-x Sn 3 x缓冲层有利于异质外延 膜的生长，并且作为可以在结构上符合并吸收由 更硬的Si和Si-Ge-Sn材料。 使用提供高纯度半导体级材料的新的高产率法制备SiH 3 GeH 3 N 3种类。

公开(公告)号：US20040251473A1

公开(公告)日：2004-12-16

申请号：US10882220

申请日：2004-07-02

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Akira Asai ,  Teruhito Ohnishi ,  Takeshi Takagi

IPC分类号： H01L031/0328

CPC分类号： H01L29/66242 ,  H01L29/1004 ,  H01L29/36 ,  H01L29/7378 ,  Y10S438/936

摘要： A SiGe spacer layer 151, a graded SiGe base layer 152 including boron, and an Si-cap layer 153 are sequentially grown through epitaxial growth over a collector layer 102 on an Si substrate. A second deposited oxide film 112 having a base opening portion 118 and a Pnull polysilicon layer 115 that will be made into an emitter connecting electrode filling the base opening portion are formed on the Si-cap layer 153, and an emitter diffusion layer 153a is formed by diffusing phosphorus into the Si-cap layer 153. When the Si-cap layer 153 is grown, by allowing the Si-cap layer 153 to include boron only at the upper part thereof by in-situ doping, the width of a depletion layer 154 is narrowed and a recombination current is reduced, thereby making it possible to improve the linearity of the current characteristics.

摘要翻译： 通过在Si衬底上的集电极层102上的外延生长，顺序地生长SiGe间隔层151，包括硼的梯度SiGe基极层152和Si覆盖层153。 在Si覆盖层153上形成第二沉积氧化物膜112，该第二沉积氧化物膜112具有基底开口部分118和将形成填充基部开口部分的发射极连接电极的P +多晶硅层115，形成发射极扩散层153a 通过将磷扩散到Si覆盖层153中。当Si覆盖层153生长时，通过原位掺杂使Si覆盖层153仅在其上部包含硼，则耗尽层的宽度 154变窄，并且复合电流降低，从而可以提高电流特性的线性。

公开(公告)号：US20030119288A1

公开(公告)日：2003-06-26

申请号：US10234520

申请日：2002-09-05

申请人： Hitachi Kokusai Electric Inc.

发明人： Hirohisa Yamazaki ,  Takaaki Noda

IPC分类号： H01L021/22 ,  H01L021/38

CPC分类号： C23C16/45574 ,  C23C16/30 ,  C23C16/45578 ,  C30B25/02 ,  C30B29/52 ,  H01L21/67017 ,  Y10S438/933 ,  Y10S438/935 ,  Y10S438/936

摘要： A substrate processing apparatus for forming a boron doped silicon-germanium film on one or more substrates in a reaction furnace of a low pressure CVD apparatus uses a mixture gas of GeH4 and SiH4 as a reaction gas, and BCl3 as a doping gas. The substrate processing apparatus includes a plurality of gas outlets for supplying GeH4 at different locations in the reaction tube and a doping gas line for supplying BCl3 at least at an upstream side of gas flow in the reaction tube.

摘要翻译： 在低压CVD装置的反应炉中，在一个或多个基板上形成硼掺杂的硅 - 锗膜的基板处理装置使用GeH 4和SiH 4的混合气体作为反应气体，BCl3作为掺杂气体。 基板处理装置包括用于在反应管中的不同位置处供给GeH 4的多个气体出口和用于至少在反应管中的气流的上游侧供给BCl 3的掺杂气体管线。

公开(公告)号：US20020151101A1

公开(公告)日：2002-10-17

申请号：US10112088

申请日：2002-03-29

申请人： The Penn State Research Foundation

发明人： Thomas N. Jackson

IPC分类号： H01L051/40

CPC分类号： C23C14/225 ,  B82Y10/00 ,  B82Y30/00 ,  H01L21/32051 ,  Y10S438/936

摘要： There is a method for forming a multilayer electronic device. The method has the following steps: a) depositing a thin molecular layer on an electrically conductive substrate and b) depositing metal atoms or ions on the thin molecular layer at an angle of about 60 degrees or less with respect to the plane of the exposed surface of the thin molecular layer.

摘要翻译： 存在形成多层电子器件的方法。 该方法具有以下步骤：a）在导电基底上沉积薄分子层，和b）相对于暴露表面的平面以约60度或更小的角度在薄分子层上沉积金属原子或离子 的薄分子层。

公开(公告)号：US6166976A

公开(公告)日：2000-12-26

申请号：US418959

申请日：1999-10-15

申请人： Adrian E. Ong

发明人： Adrian E. Ong

IPC分类号： G11C7/12 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C7/12 ,  H01L27/10897 ,  Y10S438/936

摘要： According to one embodiment, a memory device comprises a bit line operable to access a memory cell. The bit line has a first end and a second end. A first equilibration circuit is coupled to the first end of the bit line, and a second equilibration circuit is coupled to the second end of the bit line. The first and second equilibration circuits cooperate to pre-charge the bit line. According to another embodiment, an embedded-process memory device comprises a p-well and a deep n-well formed into a substrate. A retrograde well is formed into the deep n-well. An equilibration circuit for pre-charging a bit line is formed into the retrograde well.

公开(公告)号：US5714777A

公开(公告)日：1998-02-03

申请号：US803033

申请日：1997-02-19

申请人： Khalid EzzEldin Ismail ,  Bernard S. Meyerson

发明人： Khalid EzzEldin Ismail ,  Bernard S. Meyerson

IPC分类号： H01L29/80 ,  H01L21/337 ,  H01L29/10 ,  H01L29/808 ,  H01L21/20

CPC分类号： H01L29/66916 ,  H01L29/1058 ,  H01L29/8083 ,  H01L29/8086 ,  Y10S438/936

摘要： A junction field effect transistor and method for making is described incorporating horizontal semiconductor layers within an opening to form a channel and a semiconductor layer through which the opening was made which forms a gate electrode surrounding the channel. The horizontal semiconductor layers may be a SiGe alloy with graded composition near the source and drain. The invention overcomes the problem of forming low resistance JFET's and provides a gate length that is easily scaleable to submicron dimensions for rf, microwave, millimeter and logic circuits without short channel effects.

摘要翻译： 描述了一种结型场效应晶体管及其制造方法，其在开口内结合有水平半导体层以形成通道，半导体层通过该半导体层形成围绕通道的栅电极。 水平半导体层可以是在源极和漏极附近具有渐变组成的SiGe合金。 本发明克服了形成低电阻JFET的问题，并且提供了对于没有短沟道效应的rf，微波，毫米波和逻辑电路，可以容易地缩放到亚微米尺寸的栅极长度。

公开(公告)号：US5656514A

公开(公告)日：1997-08-12

申请号：US346209

申请日：1994-11-22

申请人： David Ahlgren ,  Jack Chu ,  Martin Revitz ,  Paul Ronsheim ,  Mary Saccamango ,  David Sunderland

发明人： David Ahlgren ,  Jack Chu ,  Martin Revitz ,  Paul Ronsheim ,  Mary Saccamango ,  David Sunderland

IPC分类号： H01L29/165 ,  H01L21/331 ,  H01L29/73 ,  H01L29/737 ,  H01L21/265

CPC分类号： H01L29/66242 ,  Y10S438/936

摘要： A high gain, high frequency transistor is formed having a combination of a moderately doped retrograde emitter and a collector which is formed by self-aligned implantation through an emitter opening window. This combination allows continued base width scaling and ensures high current capability yet limits the electric field at the emitter-base junction, particularly near the base contacts, in order to reduce leakage and capacitance and to enhance breakdown voltage. Cut-off frequencies on the order of 100 GHz can thus be obtained in the performance of a transistor with a 30 nm base width in a SiGe device.

摘要翻译： 形成高增益高频晶体管，其具有中等掺杂逆向发射极和通过发射器开口窗口的自对准注入形成的集电极的组合。 这种组合允许持续的基底宽度缩放并确保高电流能力，但是限制了发射极 - 基极结处，特别是靠近基极触点处的电场，以便减少泄漏和电容并增强击穿电压。 因此，在SiGe器件中，具有30nm基极宽度的晶体管的性能可获得大约100GHz的截止频率。

公开(公告)号：US5571732A

公开(公告)日：1996-11-05

申请号：US474272

申请日：1995-06-07

申请人： William U. Liu

发明人： William U. Liu

IPC分类号： H01L21/331 ,  H01L29/737 ,  H01L21/265

CPC分类号： H01L29/66318 ,  H01L29/7371 ,  Y10S148/072 ,  Y10S438/936

摘要： In one form of the invention, a bipolar transistor is disclosed, the transistor comprising a GaAs substrate in the (111) orientation 100, and an InGaAs region 106 over the substrate 100, the InGaAs region 106 having a first surface and a second surface, wherein the mole fraction of In in the InGaAs region 106 varies from said first surface to said second surface.

摘要翻译： 在本发明的一种形式中，公开了一种双极晶体管，该晶体管包括（111）取向为100的GaAs衬底和衬底100上的InGaAs区域106，具有第一表面和第二表面的InGaAs区域106， 其中InGaAs区域106中的In的摩尔分数从所述第一表面到所述第二表面变化。

公开(公告)号：US5366927A

公开(公告)日：1994-11-22

申请号：US128634

申请日：1993-09-28

申请人： Jan F. Schetzina

发明人： Jan F. Schetzina

IPC分类号： H01L21/443 ,  H01L33/00 ,  H01L33/28 ,  H01L33/40 ,  H01S5/02 ,  H01S5/042 ,  H01S5/183 ,  H01S5/327 ,  H01L21/20

CPC分类号： H01L33/40 ,  B82Y20/00 ,  H01L21/443 ,  H01L33/0083 ,  H01L33/28 ,  H01S5/0421 ,  H01S5/0215 ,  H01S5/183 ,  H01S5/3095 ,  H01S5/3215 ,  H01S5/327 ,  H01S5/347 ,  Y10S148/064 ,  Y10S438/936

摘要： An ohmic contact to a p-type zinc selenide (ZnSe) layer in a Group II-VI semiconductor device, includes a zinc telluride selenide (ZnTe.sub.x Se.sub.1-x) layer on the zinc selenide layer, a mercury selenide (HgSe) layer on the zinc telluride selenide layer and a conductor (such as metal) layer on the mercury selenide layer. The zinc telluride selenide and mercury selenide layers between the p-type zinc selenide and the conductor layer provide an ohmic contact by eliminating the band offset between the wide bandgap zinc selenide and the conductor. Step graded, linear graded, and parabolic graded layers of zinc telluride selenide may be provided. An integrated heterostructure is formed by epitaxially depositing the ohmic contact on the Group II-VI device. A removable overcoat layer may be formed on the Group II-VI device to allow room temperature atmospheric pressure transfer of the device from a zinc based deposition chamber to a mercury based deposition chamber, for deposition of the ohmic contact. A large area emitter may be formed by limiting the thickness of the mercury selenide layer so that optical radiation passes therethrough. A high efficiency optical emitter may be provided by using zinc telluride selenide or zinc sulfur telluride selenide to form an isoelectronic trap which produces broad and intense light output in the blue/green region.

摘要翻译： 与II-VI族半导体器件中的p型硒化锌（ZnSe）层的欧姆接触包括在硒化锌层上的碲化锌硒化锌（ZnTexSe1-x）层，锌上的汞硒化物（HgSe）层 硒化碲层和汞硒化物层上的导体（如金属）层。 p型硒化锌与导体层之间的碲化锌硒化物和硒化汞层通过消除宽带隙硒化锌与导体之间的带偏移而提供欧姆接触。 可以提供步骤分级，线性分级和碲化锌硒化物的抛物线分级层。 通过外延沉积II-VI族元件上的欧姆接触来形成集成的异质结构。 可以在II-VI族装置上形成可移除的外涂层，以使装置的室温大气压力从锌基沉积室转移到基于汞的沉积室，用于沉积欧姆接触。 可以通过限制硒化汞层的厚度使得光学辐射通过其中而形成大面积发射极。 可以通过使用碲化镉硒或碲化碲硒化物来形成高效光发射器，以形成在蓝/绿区域产生宽而强的光输出的等电子阱。

公开(公告)号：US5352912A

公开(公告)日：1994-10-04

申请号：US792493

申请日：1991-11-13

申请人： Emmanuel F. Crabbe ,  David L. Harame ,  Bernard S. Meyerson ,  Gary Patton ,  Johannes M. C. Stork

发明人： Emmanuel F. Crabbe ,  David L. Harame ,  Bernard S. Meyerson ,  Gary Patton ,  Johannes M. C. Stork

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L29/165 ,  H01L29/737 ,  H01L29/161 ,  H01L29/72

CPC分类号： H01L29/7378 ,  H01L29/737 ,  Y10S438/936

摘要： A heterojunction bipolar transistor having a single-crystal emitter with reduced charge storage and acceptable current gain is described herein. The heterojunction transistor comprises a collector region, a base region formed on the collector region, and a single-crystal emitter region grown on the base region by low temperature epitaxy. During the formation of the base region, a graded profile of 5-23% germanium is added to the base, as the distance to the collector region decreases, thereby decreasing the base bandgap as it approaches the collector region. Further, during the formation of the emitter region, a graded profile of 0-20% germanium is added to the emitter as the distance from the emitter-base junction increases. Thus, the emitter bandgap decreases as it moves farther from the emitter-base junction. The result of the above grading profiles is that the emitter bandgap is narrower at the emitter contact than the base bandgap at the emitter-base junction.

摘要翻译： 本文描述了具有具有降低的电荷存储和可接受的电流增益的单晶发射极的异质结双极晶体管。 异质结晶体管包括集电极区域，形成在集电极区域上的基极区域和通过低温外延生长在基极区域上的单晶发射极区域。 在形成基极区域时，随着到集电极区域的距离减小，5-23％的锗的梯度分布被添加到基极中，从而随着接近集电极区域而减小基带隙。 此外，在形成发射极区域期间，随着与发射极 - 基极结的距离增加，0-20％锗的梯度轮廓被添加到发射极。 因此，发射极带隙随着与发射极 - 基极结更远地移动而减小。 上述分级曲线的结果是，在发射极接触处的发射极带隙比发射极 - 基极结处的基极带隙更窄。