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公开(公告)号：US11888417B2
公开(公告)日：2024-01-30
申请号：US17710726
申请日：2022-03-31
Applicant: Huawei Digital Power Technologies Co., Ltd.
Inventor： Zhaoxue Cui , Wei Zhang , Ningbo Feng
Abstract: An energy conversion apparatus, a motor, a power system, and a vehicle are provided. The energy conversion apparatus may integrate a motor drive function by using a three-phase bridge arm converter and a motor winding, and integrate an alternating current charging function by using a two-phase two-bridge-arm converter and a transformer. In this way, the energy conversion apparatus can integrate the charging function and the motor drive function. When the energy conversion apparatus is installed on an electric vehicle, a vehicle integration level can be increased, a structure layout of the electric vehicle can be simplified, and costs and a volume of the electric vehicle can be reduced.
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公开(公告)号：US11881854B2
公开(公告)日：2024-01-23
申请号：US18163273
申请日：2023-02-01
Applicant: uPI Semiconductor Corp.
Inventor： Shao-Lin Feng
CPC classification number: H03K19/018507 , H03K3/037 , H03K19/20 , H03K3/017 , H03K5/01 , H03K2005/00013
Abstract: A level shifter circuit of a driving device includes first and second pulse generators, first and second level shifters, and a determination circuit. The first pulse generator provides a first input signal according to a high-voltage signal. The first input signal includes a pulse signal having a first current level and a sustain signal having a second current level following the pulse signal. The first level shifter receives the first input signal to generate a first indication signal. The second pulse generator provides a second input signal according to the high-voltage signal. The second input signal includes the pulse signal and the sustain signal following the pulse signal. The second level shifter receives the second input signal to generate a second indication signal. The determination circuit generates a low-voltage signal according to the first indication signal and the second indication signal.
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公开(公告)号：US20240007091A1
公开(公告)日：2024-01-04
申请号：US18367911
申请日：2023-09-13
Applicant: Texas Instruments Incorporated
Inventor： Madusudanan Srinivasan Gopalan , Christopher Schell , Benyong Zhang
CPC classification number: H03K5/01 , H03K3/037 , H03K21/02 , G06F1/12 , H03K2005/00058
Abstract: A clock generator circuit including an integer divider, having a first input receiving a reference clock and configured to generate an intermediate clock at a frequency divided down from a frequency of the reference clock by an integer value, a digital delay stage configured to generate a delayed intermediate clock delayed from the intermediate clock by a number of fractional cycles of the reference clock selected responsive to a fractional cycle value, and an analog delay stage configured to generate an output clock delayed from the delayed intermediate clock by a delay value selected responsive to a fine adjustment value. The clock generator circuit further includes math engine circuitry configured to compute a phase adjustment code responsive to the phase adjustment word, the phase adjustment code comprising the integer value, the fractional cycle value, and the fine adjustment value. The clock generator circuit may be implemented in a clock domain of a system along with one or more other clock generator circuits that each generate an output clock based on a reference clock generated by a reference clock source, such as a phase-locked loop.
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公开(公告)号：US11863179B2
公开(公告)日：2024-01-02
申请号：US17688989
申请日：2022-03-08
Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
Inventor： Kangling Ji
IPC: H03K19/0185 , H03K3/037
CPC classification number: H03K19/018521 , H03K3/037
Abstract: A voltage conversion circuit is provided. The circuit includes a first input module and a second input module. The first input module is connected to a first voltage and has a first input terminal for receiving an input signal and outputting a conversion signal, a high level of the input signal is a second voltage which is less than the first voltage; The second input module is connected to the first input module and has a second input terminal and an output terminal, the second input terminal is configured to receive a sampling signal, and the second input module is configured to sample the conversion signal according to the sampling signal and output an output signal via the output terminal.
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公开(公告)号：US11848672B2
公开(公告)日：2023-12-19
申请号：US17719004
申请日：2022-04-12
Applicant: STMicroelectronics International N.V.
Inventor： Sandeep Jain , Jeena Mary George
IPC: H03K19/23 , G01R31/3185 , H03K19/20 , H03K19/00 , H03K3/037
CPC classification number: H03K19/23 , G01R31/318525 , G01R31/318536 , H03K3/037 , H03K19/0021 , H03K19/20
Abstract: In an embodiment, an integrated circuit includes: a voting circuit including N scan flip-flops, where N is an odd number greater than or equal to 3, and where the N scan flip-flops includes a first scan flip-flop and a second scan flip-flop, where an output of the first scan flip-flop is coupled to a scan input of the second scan flip-flop; a scan chain including the N scan flip-flops of the voting circuit, and third and fourth scan flip-flops, the scan chain configured to receive a scan enable signal; and a scan enable control circuit configured to control a scan enable input of the first or second scan flip-flops based on the scan enable signal and based on a scan input of the third scan flip-flop or an output of the fourth scan flip-flop.
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Patent Agency Ranking
公开(公告)号：US11848644B2
公开(公告)日：2023-12-19
申请号：US18131872
申请日：2023-04-07
Applicant: LANSUS TECHNOLOGIES INC.
Inventor： Xiaojiao Ren , Jiashuai Guo
Abstract: A resistor-capacitor oscillation circuit includes a first group of inverters, a second group of inverters, a latch, a delay circuit, and a third group of inverters. The first group of the inverters is connected to the delay circuit and is configured to generate a first signal A and a second signal B. An input end of the second group of the inverters is connected to an enable signal EN. An output end of the second group of the inverters is connected to the latch. An output end of the delay circuit is connected to the latch. The latch is connected to the third group of the inverters and includes a first output end and a second output end. After a first clock signal FB is driven by the third group of the inverters, an output signal CLK is output by an output end of the third group.
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公开(公告)号：US20230403016A1
公开(公告)日：2023-12-14
申请号：US17746729
申请日：2022-05-17
Applicant: Apple Inc.
Inventor： Ali Parsa , Ahmed I. Hussein
Abstract: This disclosure is directed towards systems and methods that improve bandwidth shifting operations of an ADPLL without losing a lock of the ADPLL and having the benefit of being able to change the bandwidth an unlimited amount of times. Indeed, a processor may transmit amplification parameters to the ADPLL to implement a bandwidth shift. The shift may occur in response to a enable signal, such as a gear trigger control signal (gear_retime signal) or a enable signal generated to cause alignment of the shifting with a clock signal (e.g., enable signal generated by AND logic gates). These systems and methods described herein many enable multiple bandwidth changing operations to occur without compromising the complexity and footprint of the system.
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公开(公告)号：US11843375B2
公开(公告)日：2023-12-12
申请号：US17968861
申请日：2022-10-19
Applicant: Kioxia Corporation
Inventor： Toshihiro Yagi
IPC: H03L5/00 , H03K3/037 , H03K3/356 , H03K19/003 , H03K19/0185
CPC classification number: H03K19/018521
Abstract: A semiconductor integrated circuit of embodiments includes a first MOS transistor configured to control conduction and non-conduction between a reference voltage point and a node, a second MOS transistor connected to the first MOS transistor via the node and configured to apply a voltage equal to or lower than a withstand voltage of the first MOS transistor to the node, a third MOS transistor configured to receive supply of a second voltage higher than the first voltage, and output an output signal of a signal level corresponding to a voltage range of the second voltage, and a switch circuit configured to make a voltage of the node a fixed voltage when the first MOS transistor is in an OFF state.
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79.发明公开公开(公告)号：US20230396252A1
公开(公告)日：2023-12-07
申请号：US18447369
申请日：2023-08-10
Inventor： Jerrin Pathrose Vareed , Shiba Mohanty
IPC: H03K19/0185 , H03K3/037
CPC classification number: H03K19/018521 , H03K3/037
Abstract: A semiconductor device includes an input, a level shifter, an output, and a switch module. The input is configured to receive an input signal in a first voltage domain. The level shifter is connected to the input and is configured to shift the input signal from the first voltage domain to a second voltage domain. The switch module is configured to connect one of the input and the level shifter to the output. A method of mitigating a delay between input and output signals of the semiconductor device is also disclosed.
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80.发明公开公开(公告)号：US20230396249A1
公开(公告)日：2023-12-07
申请号：US17834669
申请日：2022-06-07
Applicant: Intel Corporation
Inventor： Terry Remple
CPC classification number: H03K19/0016 , H03K3/037 , H03K5/14 , H03K19/21 , H03K2005/00013
Abstract: Techniques and mechanisms for using multiple delay line circuits to detect a change to the frequency of a periodic signal. In an embodiment, a first delay line receives the periodic signal from a phase locked loop, and generates first bits which include an indication of a first edge segment of the delay line. Another two delay lines receive respective bits which are variously based on a sampling of the first bits. The other two delay lines each output a respective one of two bit sequences, which are sampled or otherwise used to determine the transitioning of a clock signal. In another embodiment, the frequency of the clock signal is determined based on one of a threshold minimum period of time that the frequency of the periodic signal is stable, a threshold minimum frequency of the periodic signal, or a threshold minimum increase to the frequency of the periodic signal.
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