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公开(公告)号：US10917227B2
公开(公告)日：2021-02-09
申请号：US16555467
申请日：2019-08-29
发明人： Xitong Ma , Ran Duan , Lihua Geng , Yanfu Li
摘要： The present disclosure provides a data transmission method, includes: multiplying a frequency of a basic clock, so as to obtain a frequency-multiplied clock, in which a maximum number of high levels in the frequency-multiplied clock is greater than a maximum numerical value that the bit number can represent; removing an invalid bit width from the data to be transmitted, and determining a bit number of an effective bit width thereof and a numerical value represented by the effective bit width; determining a data period, according to the bit number of the effective bit width in the data to be transmitted; determining an actual number of high levels, according to a numerical value represented by the effective bit width in the data to be transmitted; and transmitting the data to be transmitted based on the frequency-multiplied clock, according to the data period and the actual number of the high levels.
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公开(公告)号：US10911165B1
公开(公告)日：2021-02-02
申请号：US16724888
申请日：2019-12-23
发明人： Siegfried Albel , Michael Aichner , Reinhard-Wolfgang Jungmaier , Dennis Noppeney , Christoph Rumpler , Saverio Trotta
摘要： In accordance with an embodiment, a method includes: receiving, by an adjustable frequency doubling circuit, a first clock signal having a first clock frequency; using the adjustable frequency doubling circuit, generating a second clock signal having a second clock frequency that is twice the first clock frequency; measuring a duty cycle parameter of the second clock signal, where the duty cycle parameter is dependent on a duty cycle of the first clock signal or a duty cycle of the second clock signal; and using the adjustable frequency doubling circuit, adjusting the duty cycle of the first clock signal or the second clock signal based on the measuring.
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公开(公告)号：US10911052B2
公开(公告)日：2021-02-02
申请号：US16421376
申请日：2019-05-23
IPC分类号： H03L7/081 , H04L27/227 , G04F10/00 , G06F1/06 , G06F1/12 , G06F1/10 , H04L25/49 , H04L7/033 , H04L27/38 , H04L7/00
摘要： A system for retiming a multi-level signal that forms an eye diagram when plotted, such as a PAM4 signal that includes an equalizer configured to create an equalized signal and a first amplifier configured to amplify the equalized signal, responsive to a first amplifier control signal, to create a first amplified signal, and a second amplifier configured to amplify the equalized signal, responsive to a second amplifier control signal, to create a second amplified signal. An eye monitor processes the equalized signal, the first amplified signal, and the second amplified signal to create a first retiming clock phase signal and a second retiming clock phase signal, which control sampling times for flip-flops. One or more delays and one or more emphasis modules are configured to delay and introduce emphasis into an output from the flip-flops, the resulting signals are combined in a summing junction to create the retimed signal.
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公开(公告)号：US10897477B2
公开(公告)日：2021-01-19
申请号：US15200896
申请日：2016-07-01
发明人： Tomas Motos , Khanh Tuan Le
摘要： A method of relay-attack resistant communications in a wireless communications system that includes a master wireless device (Master) sending a synchronization signal to a slave wireless device (Slave). The synchronization signal includes timing information including a common time reference and a timeslot duration for interlocking Master communication timeslots for Master and Slave communication timeslots so that an alternating TX and RX role pattern is provided. The Master analyzes Slave packet data received from the Slave to identify overlaps of a transmission from the Master and the slave packet data, and in a case of detecting overlap, suspends communications from Master to Slave to prevent a relay-attack.
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公开(公告)号：US20210013889A1
公开(公告)日：2021-01-14
申请号：US16946957
申请日：2020-07-13
申请人： Sanjole Inc.
发明人： Joseph M. Fala , Hao Liu
摘要： A system, circuit and method for providing a controlled oscillator frequency with reduced phase noise for use in a communication system. In one embodiment, the circuit includes a delay line coupled to an output of a voltage controlled oscillator (“VCO”). The circuit also includes a combiner having a first input coupled to an output of the delay line, and a second input coupled to the output of the VCO. An output of the combiner is coupled to a control input of the VCO.
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公开(公告)号：US10892841B2
公开(公告)日：2021-01-12
申请号：US16438849
申请日：2019-06-12
发明人： Leo Aichriedler
摘要： A sensor may determine a sampling pattern based on a group of synchronization signals received by the sensor. The sampling pattern may identify an expected time for receiving an upcoming synchronization signal. The sensor may trigger, based on the sampling pattern, a performance of a sensor operation associated with the upcoming synchronization signal. The performance of the sensor operation may be triggered before the upcoming synchronization signal is received.
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公开(公告)号：US20210006440A1
公开(公告)日：2021-01-07
申请号：US17028834
申请日：2020-09-22
申请人： Kandou Labs SA
发明人： Ali Hormati , Richard Simpson
摘要： Methods and systems are described for generating two comparator outputs by comparing a received signal to a first threshold and a second threshold according to a sampling clock, the first and second thresholds determined by an estimated amount of inter-symbol interference on a multi-wire bus, selecting one of the two comparator outputs as a data decision, the selection based on at least one prior data decision, and selecting one of the two comparator outputs as a phase-error decision, the phase error decision selected in response to identification of a predetermined data decision pattern.
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78.发明申请公开(公告)号：US20200344038A1
公开(公告)日：2020-10-29
申请号：US16391527
申请日：2019-04-23
申请人： Ciena Corporation
发明人： Sadok Aouini , Naim Ben-Hamida , Ahmad Abdo , Timothy James Creasy , Lukas Jakober , Yalmez M.A. Yazaw , Shahab Oveis Gharan
IPC分类号： H04L7/033 , H04B10/071 , H04B10/079 , H04B10/25 , H04B10/40
摘要： A system includes an optical transmitter including a transmitter Phase Lock Loop (PLL) circuit; an optical receiver connected to the optical transmitter and including a receiver PLL circuit; and circuitry configured to inject a test stimulus to a clock causing jitter in one of the transmitter PLL circuitry and the receiver PLL circuit, wherein the test stimulus is set for characterizing the jitter tolerance of optical receiver. As well, a circuit that injects SOP transient at the transmitter is included. It is configured to test the tolerance of optical receiver to handle fast change in the SOP state. The optical receiver is configured to determine if the system is operational at a jitter value due to the test stimulus based on compliance to one or more thresholds including any of a target Bit Error Rate, a Forward-Error-Correction (FEC) hit, and a jitter Root Mean Square (RMS).
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公开(公告)号：US20200336288A1
公开(公告)日：2020-10-22
申请号：US16916968
申请日：2020-06-30
IPC分类号： H04L7/033
摘要： A signal conditioner for use in a serial data communications link. The signal conditioner including a tunable delay element responsive to a tuning signal to provide time domain delay modulation of the input data signals to generate conditioned (output) data signals, and phase comparator circuitry to generate the delay tuning signal based on a detected phase error between feedback conditioned data signals, and a reference signal. The tunable delay element and the phase comparator circuitry forming a delay-locked tuning loop to phase lock the conditioned data signals to the reference signal, independent of voltage domain frequency response. An example signal conditioner is a jitter attenuator/cleaner, where the bandwidth of the reference signal is lower than the bandwidth of the delay-locked tuning loop, to provide a low-jitter reference signal.
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公开(公告)号：US10804797B1
公开(公告)日：2020-10-13
申请号：US16284633
申请日：2019-02-25
申请人： INPHI CORPORATION
摘要： The present invention is directed to electrical circuits. According to an embodiment, the present invention provides a charge pump circuit with a bias section and a switch section. The switch section includes a first switch coupled to an early signal and a second switch coupled to a late signal. The charge pump additionally includes a low-pass filter. The switch section includes a first resistor and a second resistor. The first resistor is directly coupled to the first switch and the low-pass filter. The second resistor is directly coupled to the second switch and the first resistor. There are other embodiments as well.
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