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543 条记录 (耗时 0.029 秒)

    LEVEL-UP SHIFTER CIRCUIT
    81.
    发明申请
    LEVEL-UP SHIFTER CIRCUIT 有权
    电平更换电路

    公开(公告)号：US20140084985A1

    公开(公告)日：2014-03-27

    申请号：US13968523

    申请日：2013-08-16

    申请人： Cavium, Inc.

    发明人： David Lin

    IPC分类号： H03K3/356

    CPC分类号： H03K3/356 ,  H03K19/0013 ,  H03K19/0185 ,  H03K19/018571

    摘要： A level-up shifter circuit is suitable for high speed and low power applications. The circuit dissipates almost no static power, or leakage current, compared to conventional designs and can preserve the signal's duty cycle even at high data rates. This circuit can be used with a wide range of power supplies while maintaining operational integrity.

    摘要翻译： 电平转换电路适用于高速和低功耗应用。 与常规设计相比，该电路几乎不会消耗静态功耗或漏电流，并且即使在高数据速率下也能保持信号的占空比。 该电路可以与广泛的电源一起使用，同时保持运行完整性。

    System and method for secure device key storage
    82.
    发明授权
    System and method for secure device key storage 有权
    用于安全设备密钥存储的系统和方法

    公开(公告)号：US08661266B2

    公开(公告)日：2014-02-25

    申请号：US13090882

    申请日：2011-04-20

    申请人： Harri Hakkarainen ,  Amer Haider ,  Muhammad Hussain ,  Trent Parker

    发明人： Harri Hakkarainen ,  Amer Haider ,  Muhammad Hussain ,  Trent Parker

    IPC分类号： G06F11/30

    CPC分类号： G06F21/10 ,  G06F2221/0704

    摘要： Disclosed are systems and methods for protecting secret device keys, such as High-bandwidth Digital Content Protection (HDCP) device keys. Instead of storing secret device keys in the plain, a security algorithm and one or more protection keys are stored on the device. The security algorithm is applied to the secret device keys and the one or more protection keys to produce encrypted secret device keys. The encrypted secret device keys are then stored either on chip or off-chip.

    摘要翻译： 公开了用于保护秘密设备密钥的系统和方法，例如高带宽数字内容保护（HDCP）设备密钥。 代替将秘密设备密钥存储在平原中，安全算法和一个或多个保护密钥被存储在设备上。 安全算法被应用于秘密设备密钥和一个或多个保护密钥以产生加密的秘密设备密钥。 然后将加密的秘密设备密钥存储在芯片上或芯片外。

    DUPLICATION IN DECISION TREES
    84.
    发明申请
    DUPLICATION IN DECISION TREES 有权
    判决书中的重复

    公开(公告)号：US20130232104A1

    公开(公告)日：2013-09-05

    申请号：US13831487

    申请日：2013-03-14

    申请人： CAVIUM, INC.

    发明人： Rajan Goyal ,  Kenneth A. Bullis ,  Satyanarayana Lakshmipathi Billa

    IPC分类号： G06N5/02

    CPC分类号： G06N5/02

    摘要： A packet classification system, apparatus, and corresponding apparatus are provided for enabling packet classification. A processor of a security appliance coupled to a network uses a classifier table having a plurality of rules, the plurality of rules having at least one field, to build a decision tree structure for packet classification. Duplication in the decision tree may be identified, producing a wider, shallower decision tree that may result in shorter search times with reduced memory requirements for storing the decision tree. A number of operations needed to identify duplication in the decision tree may be reduced, thereby increasing speed and efficiency of a compiler building the decision tree.

    摘要翻译： 提供了分组分类系统，装置和相应的装置，用于使分组分类。 耦合到网络的安全设备的处理器使用具有多个规则的分类器表，所述多个规则具有至少一个字段，以构建用于分组分类的决策树结构。 可以识别决策树中的重复，产生更宽，更浅的决策树，其可以导致缩短的搜索时间，同时减少用于存储决策树的存储器需求。 可以减少在决策树中识别重复所需的多个操作，从而提高构建决策树的编译器的速度和效率。

    Differential amplifier with duty cycle compensation
    85.
    发明授权
    Differential amplifier with duty cycle compensation 有权
    带占空比补偿的差分放大器

    公开(公告)号：US08519785B2

    公开(公告)日：2013-08-27

    申请号：US13369562

    申请日：2012-02-09

    申请人： Scott Meninger

    发明人： Scott Meninger

    IPC分类号： H03F3/45

    CPC分类号： H03F1/3223 ,  H03F2203/45138

    摘要： A differential amplifier replicates the input stage and cross-connects the inputs, so that the input-to-output delay will be balanced in an averaged sense. The outputs of each of the two input stages are then summed after an open loop delay matched inversion has taken place. The result is a reduction in the duty cycle distortion of the receiver amplifier over process voltage and temperature (PVT) variation. This is enabled by the fact that a full swing CMOS delay cell can be made to have good delay matching over PVT, whereas the input stage to a differential amplifier may, depending on architecture, have poor delay matching because of impedance mismatches within the amplifier.

    摘要翻译： 差分放大器复制输入级并交叉连接输入，使得输入到输出延迟将以平均意义平衡。 然后，在开环延迟匹配反转发生之后，两个输入级中的每一个的输出相加。 结果是接收机放大器的工作电压和温度（PVT）变化的占空比失真减小。 这可以通过以下事实实现：可以使全摆幅CMOS延迟单元在PVT上具有良好的延迟匹配，而根据架构，差分放大器的输入级可能由于放大器内的阻抗失配而具有差的延迟匹配。

    State machine for deskew delay locked loop
    86.
    发明授权
    State machine for deskew delay locked loop 有权
    状态机用于偏移延迟锁定环

    公开(公告)号：US08513994B2

    公开(公告)日：2013-08-20

    申请号：US13369579

    申请日：2012-02-09

    申请人： Suresh Balasubramanian

    发明人： Suresh Balasubramanian

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0812 ,  H03L7/087

    摘要： A state machine for a DLL ensures a given clock (DCLK) is always locked to the rising edge of an incoming reference clock (REFCLK) through the use of two additional phase detectors. The first phase detector samples the value of DCLK a given delay prior to the rising edge of REFCLK, and the second samples the value of DCLK a given delay after the rising edge of REFCLK. The additional information provided by these two phase detectors enables a determination as to whether we are close to the falling edge of REFCLK, and, if so, add enough delay to DCLK to ensure that the DLL locks only to the rising edge of REFCLK and never accidentally to the falling edge.

    摘要翻译： 用于DLL的状态机通过使用两个附加相位检测器来确保给定时钟（DCLK）始终被锁定到输入参考时钟（REFCLK）的上升沿。 第一相位检测器在REFCLK的上升沿之前对给定延迟进行DCLK的值采样，并且在REFCLK的上升沿之后，第二相采样DCLK的值给定的延迟。 这两个相位检测器提供的附加信息可以确定我们是否接近REFCLK的下降沿，如果是，请给DCLK添加足够的延迟，以确保DLL仅锁定到REFCLK的上升沿 不小心掉到了边缘。

    REVERSE NFA GENERATION AND PROCESSING
    88.
    发明申请
    REVERSE NFA GENERATION AND PROCESSING 有权
    反向NFA生成和处理

    公开(公告)号：US20130133064A1

    公开(公告)日：2013-05-23

    申请号：US13303885

    申请日：2011-11-23

    申请人： Rajan Goyal ,  Satyanarayana Lakshmipathi Billa

    发明人： Rajan Goyal ,  Satyanarayana Lakshmipathi Billa

    IPC分类号： G06F21/00

    CPC分类号： H04L63/0254 ,  G06F17/30958 ,  H04L63/0245 ,  H04L63/1408 ,  H04L63/1416

    摘要： In a processor of a security appliance, an input of a sequence of characters is walked through a finite automata graph generated for at least one given pattern. At a marked node of the finite automata graph, if a specific type of the at least one given pattern is matched at the marked node, the input sequence of characters is processed through a reverse non-deterministic finite automata (rNFA) graph generated for the specific type of the at least one given pattern by walking the input sequence of characters backwards through the rNFA beginning from an offset of the input sequence of characters associated with the marked node. Generating the rNFA for a given pattern includes inserting processing nodes for processing an input sequence of patterns to determine a match for the given pattern. In addition, the rNFA is generated from the given type of pattern.

    摘要翻译： 在安全装置的处理器中，字符序列的输入通过为至少一个给定模式生成的有限自动机图。 在有限自动机图的标记节点处，如果在标记节点处匹配至少一个给定模式的特定类型，则通过针对该标记节点生成的反向非确定性有限自动机（rNFA）图来处理输入的字符序列 通过从与所标记的节点相关联的输入字符序列的偏移开始的rNFA向后移动输入的字符序列来指定至少一个给定模式的特定类型。 为给定模式生成rNFA包括插入用于处理输入模式序列的处理节点以确定给定模式的匹配。 此外，rNFA是从给定类型的模式生成的。