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公开(公告)号：US20210135101A1
公开(公告)日：2021-05-06
申请号：US16672632
申请日：2019-11-04
发明人： Desmond Jia Jun LOY , Eng Huat TOH , Shyue Seng TAN , Steven SOSS
IPC分类号： H01L45/00
摘要： A memory device may include at least one inert electrode, at least one active electrode, an insulating element arranged at least partially between the at least one active electrode and the at least one inert electrode, and a switching element arranged under the insulating element. The switching element may be arranged at least partially between the at least one active electrode and the at least one inert electrode. The switching element may include a first end and a second end contacting the at least one active electrode; and a middle segment between the first end and the second end, where the middle segment may at least partially contact the at least one inert electrode.
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公开(公告)号：US10978510B2
公开(公告)日：2021-04-13
申请号：US16443255
申请日：2019-06-17
发明人： Pinghui Li , Haiqing Zhou , Liying Zhang , Wanbing Yi , Ming Zhu , Danny Pak-Chum Shum , Darin Chan
IPC分类号： H01L27/22 , H01L43/02 , H01L43/08 , G11C5/02 , G11C11/16 , H01L27/02 , H01L43/12 , G11C11/15
摘要： Methods of forming a MTJ dummy fill gradient across near-active-MRAM-cell periphery and far-outside-MRAM logic regions and the resulting device are provided. Embodiments include providing an embedded MRAM layout with near-active-MRAM-cell periphery logic and far-outside-MRAM logic regions; forming a MTJ structure within the layout based on minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first and second metal layers; forming a high-density MTJ dummy structure in the near-active-MRAM-cell periphery logic region based on second minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer; and forming a low-density MTJ dummy structure in the far-outside-MRAM logic region based on third minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer.
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公开(公告)号：US20210082905A1
公开(公告)日：2021-03-18
申请号：US16574184
申请日：2019-09-18
发明人： Jie ZENG , Raunak KUMAR , Kyong Jin HWANG
IPC分类号： H01L27/02 , H01L29/735 , H01L27/092
摘要： An ESD protection device may include a substrate, a first conductivity region arranged at least partially within the substrate, a second conductivity region arranged at least partially within the first conductivity region, third and fourth conductivity regions arranged at least partially within the second conductivity region, and first and second terminal portions arranged at least partially within the third and fourth conductivity regions respectively. The third and fourth conductivity regions may be spaced apart from each other. The substrate and the second conductivity region may have a first conductivity type. The first conductivity region, third conductivity region, fourth conductivity region and first and second terminal portions may have a second conductivity type different from the first conductivity type. The first and second terminal portions may have higher doping concentrations than the third and fourth conductivity regions respectively.
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公开(公告)号：US20210043637A1
公开(公告)日：2021-02-11
申请号：US16532522
申请日：2019-08-06
发明人： Desmond Jia Jun LOY , Eng Huat Toh , Bin Liu , Shyue Seng Tan
IPC分类号： H01L27/112 , H01L29/36 , H01L21/265 , H01L21/266 , H01L21/762 , H01L23/525 , G11C17/16 , G11C17/18
摘要： A memory device may include a first conductivity region, and second and third conductivity regions arranged at least partially within the first conductivity region. The first and second conductivity regions may have a different conductivity type from at least a part of the third conductivity region. The memory device may include first and second gates arranged over the third conductivity region. The second conductivity region may be coupled to a source line, and the gates may be coupled to respective word lines. When a predetermined write voltage difference is applied between the source line and a word line, an oxide layer of the gate coupled to the word line may break down to form a conductive link between the gate electrode of the gate and the third conductivity region. The memory device may have a smaller cell area, and may be capable of operating at both higher and lower voltages.
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公开(公告)号：US10903272B2
公开(公告)日：2021-01-26
申请号：US16205314
申请日：2018-11-30
发明人： Lanxiang Wang , Shyue Seng Tan , Eng Huat Toh
摘要： A memory device may include a substrate having conductivity regions and a channel region. A first voltage line may be arranged over the channel region. A second voltage line, and third and fourth voltage lines may be electrically coupled to a first conductivity region and a second conductivity region respectively. Resistive units may be arranged between the third and fourth voltage lines and the second conductivity region. In use, changes in voltages applied between the second and third voltage lines, and between the second and fourth voltage lines may cause resistances of first and second resistive units to switch between lower and higher resistance values. The lower resistance value of the first resistive unit may be different from the lower resistance value of the second resistive unit and/or the higher resistance value of the first resistive unit may be different from the higher resistance value of the second resistive unit.
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公开(公告)号：US20210013405A1
公开(公告)日：2021-01-14
申请号：US16504344
申请日：2019-07-08
IPC分类号： H01L45/00
摘要： The disclosure relates generally to resistive switching nonvolatile random access memory (ReRAM) devices, and more generally to structures and methods of fabricating multiple conductive elements in ReRAM devices. A resistive memory device is presented, the device comprising a first electrode having a first work function, and a second electrode having a second work function, the first work function being different from the second work function. A dielectric layer is disposed between the first and second electrodes. The device further comprises a set of nanocrystal structures distributed in the dielectric layer. A conductive layer is also disposed in the dielectric layer.
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公开(公告)号：US20210013166A1
公开(公告)日：2021-01-14
申请号：US16508288
申请日：2019-07-10
IPC分类号： H01L23/00
摘要： The disclosed subject matter relates to a structure and method to improve bond pad reliability of semiconductor devices. According to an aspect of the present disclosure, a bond pad structure is provided that includes a dielectric layer and at least one bond pad in the dielectric layer, wherein the bond pad has a top surface. A passivation layer has an opening over the bond pad, wherein the opening has sidewalls. A low-k barrier layer is covering the sidewalls of the opening and the top surface of the bond pad. Protective structures are formed over the sidewalls of the opening.
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公开(公告)号：US20210010997A1
公开(公告)日：2021-01-14
申请号：US16505733
申请日：2019-07-09
IPC分类号： G01N33/487 , G01N27/447
摘要： In a non-limiting embodiment, a device may include a substrate having conducting lines thereon. One or more fin structures may be arranged over the substrate. Each fin structure may include a sensor arranged over the substrate and around the fin structure. The sensor may include a self-aligned first sensing electrode and a self-aligned second sensing electrode arranged around the fin structure. The first sensing electrode and the second sensing electrode each may include a first portion lining a sidewall of the fin structure and a second portion arranged laterally from the first portion. At least the first portion of the first sensing electrode and the first portion of the second sensing electrode may define a sensing cavity of the sensor. The second portion of the first sensing electrode and the second portion of the second sensing electrode may be electrically coupled to the conducting lines.
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公开(公告)号：US10890554B1
公开(公告)日：2021-01-12
申请号：US16447312
申请日：2019-06-20
发明人： Lanxiang Wang , Eng Huat Toh , Shyue Seng Tan , Ping Zheng
IPC分类号： H01L27/148 , G01N27/414 , H01L29/423 , H01L21/84 , H01L27/12 , H01L29/78
摘要： Structures for a sensor and fabrication methods for a sensor. Features each having a top surface and a plurality of side surfaces are formed. A sensing layer is formed on the top surface and the side surfaces of each feature, and an interconnect structure having one or more interlayer dielectric layers is formed over the features. The one or more interlayer dielectric layers include a cavity arranged to expose the sensing layer, and the sensing layer is composed of a material that is sensitive to a property of an analyte solution provided in the cavity.
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公开(公告)号：US10818837B1
公开(公告)日：2020-10-27
申请号：US16407661
申请日：2019-05-09
摘要： Structures for a non-volatile memory element and methods of fabricating a structure for a non-volatile memory element. The structure includes a bottom electrode, a seed layer on the bottom electrode, and a magnetic-tunneling-junction layer stack on the seed layer. The seed layer is composed of a nickel-chromium-ruthenium alloy including ruthenium in an amount ranging from seven atomic percent by weight to eighty-four atomic percent by weight.
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