公开(公告)号：US08779754B2

公开(公告)日：2014-07-15

申请号：US13019277

申请日：2011-02-01

申请人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Eric Choong-Yin Chang ,  Peter Boyle ,  Adam J. Wright

发明人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Eric Choong-Yin Chang ,  Peter Boyle ,  Adam J. Wright

IPC分类号： H03K5/14 ,  H03K5/13 ,  H03K5/15

CPC分类号： H03K5/135 ,  G01R31/3016 ,  G01R31/31725 ,  G01R31/318516 ,  H03K5/14 ,  H03K5/1504

摘要： Delay associated with each of two signals along respective transmission paths is accurately measured using a delay measurement circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated. Thus, the measured delay associated with each of the two signals is subject to the same fabrication-dependent attributes that affect the actual circuitry through which the two signals will be propagated during operation of the device. The skew between the two signals is quantified as the difference in the measured delays. Coarse and fine delay modules are defined within the transmission path of each of the two signals. Based on the measured skew between the two signals, the coarse and fine delay modules are appropriately set to compensate for the skew. The appropriately settings for the coarse and fine delay modules can be stored in non-volatile memory elements.

摘要翻译： 使用延迟测量电路精确测量与各传输路径中的两个信号中的每一个相关的延迟，该延迟测量电路在实际设备上制造，其中制造用于传播两个信号的电路。 因此，与两个信号中的每一个相关联的测量的延迟受到影响在设备操作期间两个信号将被传播的实际电路的相同制造相关属性。 两个信号之间的偏差被量化为测量延迟的差。 在两个信号中的每一个的传输路径内定义粗略和精细的延迟模块。 基于两个信号之间的测量偏差，粗调和精细延迟模块被适当地设置以补偿偏斜。 粗略和精细延迟模块的适当设置可以存储在非易失性存储器元件中。

公开(公告)号：US08680905B1

公开(公告)日：2014-03-25

申请号：US13486670

申请日：2012-06-01

申请人： Pradeep Nagarajan ,  Yan Chong ,  Sean Shau-Tu Lu ,  Chiakang Sung ,  Joseph Huang

发明人： Pradeep Nagarajan ,  Yan Chong ,  Sean Shau-Tu Lu ,  Chiakang Sung ,  Joseph Huang

IPC分类号： H03L7/00

CPC分类号： H03L7/00 ,  G11C7/04 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254 ,  H03L7/0805 ,  H03L7/0812

摘要： A circuit includes a delay locked loop (DLL), a calibration circuit and an output delay chain controlled by the calibration circuit. The DLL comprises a plurality of series-coupled first delay elements each of which has substantially the same first delay. The calibration circuit comprises a plurality of series-coupled second delay elements, each of which has substantially the same second delay that is less than the first delay, a first delay element, and a circuit for determining the minimum number of second delay elements that are needed to produce the first delay. The output delay chain comprises a plurality of series-coupled second delay elements, an input for receiving the input signal, and a circuit for selectively tapping the output delay chain at a plurality of taps in the output delay chain so as to produce in the input signal different delays of integral multiples of the second delay.

摘要翻译： 电路包括由校准电路控制的延迟锁定环（DLL），校准电路和输出延迟链。 该DLL包括多个串联耦合的第一延迟元件，每个延迟元件具有基本上相同的第一延迟。 校准电路包括多个串联耦合的第二延迟元件，每个延迟元件具有基本相同的第二延迟小于第一延迟，第一延迟元件和用于确定第二延迟元件的最小数量的电路 需要产生第一个延迟。 输出延迟链包括多个串联耦合的第二延迟元件，用于接收输入信号的输入端和用于在输出延迟链中的多个抽头处有选择地分接输出延迟链的电路，以便产生输入 发出第二延迟的整数倍的不同延迟。

公开(公告)号：US08630131B1

公开(公告)日：2014-01-14

申请号：US13562204

申请日：2012-07-30

申请人： Wilma Shiao ,  Warren Nordyke ,  Khai Nguyen ,  Chiakang Sung

发明人： Wilma Shiao ,  Warren Nordyke ,  Khai Nguyen ,  Chiakang Sung

IPC分类号： G11C5/14 ,  G11C7/06 ,  G11C7/00 ,  G11C8/16 ,  H03K17/16 ,  H03K19/003

CPC分类号： G11C7/1087 ,  G11C5/04 ,  G11C7/1051 ,  G11C7/1093 ,  H03K19/003 ,  H03K19/17724 ,  H03K23/40

摘要： An integrated circuit may include memory interface circuitry that is used to communicate with off-chip memory. The memory interface circuitry may include data strobe (DQS) enable circuitry that receives DQS signals from the off-chip memory and that outputs a gated version of the DQS signals. The DQS enable circuitry may include an input buffer, a comparator, a latch, a flip-flop, a counter, and a gating circuit. The input buffer may receive an incoming DQS signal. The comparator may be used to determine when the incoming DQS signal starts to toggle. The latch may be used to control when a gating signal is asserted. The flip-flop controls the counter, which limits the duration that the gating signal is asserted. The gating circuit receives the DQS signal from the buffer and the gating signal and passes the DQS signal through to its output only when the gating signal is asserted.

摘要翻译： 集成电路可以包括用于与片外存储器通信的存储器接口电路。 存储器接口电路可以包括从片外存储器接收DQS信号并输出​​DQS信号的选通版本的数据选通（DQS）使能电路。 DQS使能电路可以包括输入缓冲器，比较器，锁存器，触发器，计数器和门控电路。 输入缓冲器可以接收输入的DQS信号。 比较器可用于确定输入的DQS信号何时开始切换。 锁存器可用于控制门控信号何时被断言。 触发器控制计数器，这限制了门控信号被断言的持续时间。 门控电路从缓冲器和门控信号接收DQS信号，并且只有当门控信号被断言时才将DQS信号传递到其输出。

公开(公告)号：US08531205B1

公开(公告)日：2013-09-10

申请号：US13363108

申请日：2012-01-31

申请人： Bonnie I. Wang ,  Chiakang Sung ,  Xiaobao Wang ,  Khai Nguyen ,  Joseph Huang

发明人： Bonnie I. Wang ,  Chiakang Sung ,  Xiaobao Wang ,  Khai Nguyen ,  Joseph Huang

IPC分类号： H03K17/16

CPC分类号： H03K19/0005 ,  H03K19/018585 ,  H03K19/17744 ,  H03K19/17788

摘要： One embodiment relates to a programmable output buffer which includes first and second programmable variable-impedance single-ended driver circuits and first and second termination circuits. The first termination circuit is coupled to a first output pin which is driven by the first programmable variable-impedance single-ended driver circuit, and the second termination circuit is coupled to a second output pin which is driven by the second programmable variable-impedance single-ended driver circuit. The first and second termination circuits are programmable to either provide parallel termination for a differential signal or drive single-ended signals with the parallel termination turned off. Other embodiments and features are also disclosed.

摘要翻译： 一个实施例涉及可编程输出缓冲器，其包括第一和第二可编程可变阻抗单端驱动器电路以及第一和第二终端电路。 第一终端电路耦合到由第一可编程可变阻抗单端驱动电路驱动的第一输出引脚，第二终端电路耦合到由第二可编程可变阻抗单端驱动的第二输出引脚 驱动电路。 第一和第二终端电路是可编程的，以提供用于差分信号的并行终端或者并联终端关断的驱动单端信号。 还公开了其它实施例和特征。

公开(公告)号：US08400186B1

公开(公告)日：2013-03-19

申请号：US13401562

申请日：2012-02-21

申请人： Xiaobao Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen

发明人： Xiaobao Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen

IPC分类号： H03K19/094

CPC分类号： H03K19/018578

摘要： A circuit comprises first and second differential pairs and first and second switch circuits. The first differential pair includes first and second transistors operable to generate a first output signal based on a first input signal in a single-ended mode. The second differential pair includes third and fourth transistors operable to generate a second output signal based on a second input signal in the single-ended mode. The first switch circuit is operable to block current through the second transistor in a differential mode. The second switch circuit is operable to block current through the third transistor in the differential mode. The first and the fourth transistors are operable to generate a third output signal based on a third input signal in the differential mode.

摘要翻译： 电路包括第一和第二差分对以及第一和第二开关电路。 第一差分对包括可操作以基于单端模式中的第一输入信号产生第一输出信号的第一和第二晶体管。 第二差分对包括第三和第四晶体管，其可操作以基于单端模式中的第二输入信号产生第二输出信号。 第一开关电路可操作以在差分模式下阻断通过第二晶体管的电流。 第二开关电路可操作以在差分模式下阻断通过第三晶体管的电流。 第一和第四晶体管可操作以基于差分模式中的第三输入信号产生第三输出信号。

公开(公告)号：US08159277B1

公开(公告)日：2012-04-17

申请号：US13031129

申请日：2011-02-18

申请人： Pradeep Nagarajan ,  Yan Chong ,  Chiakang Sung ,  Joseph Huang

发明人： Pradeep Nagarajan ,  Yan Chong ,  Chiakang Sung ,  Joseph Huang

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03K5/133 ,  H03K2005/00058

摘要： A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic signal. Each of the delay circuits includes variable delay blocks and fixed delay blocks that are coupled to form at least two delay paths for an input signal through the delay circuit to generate a delayed output signal. Delays of the variable delay blocks in the delay circuits vary based on the output signal of the phase detector. Each of the delay circuits reroutes the input signal through a different one of the delay paths to generate the delayed output signal based on the output signal of the phase detector during operation of the feedback loop circuit.

摘要翻译： 反馈回路包括相位检测器和延迟电路。 相位检测器基于延迟周期信号产生输出信号。 延迟电路在延迟链中耦合，延迟链延迟了延迟的周期信号。 每个延迟电路包括可变延迟块和固定延迟块，其被耦合以形成用于通过延迟电路的输入信号的至少两个延迟路径以产生延迟的输出信号。 延迟电路中的可变延迟块的延迟基于相位检测器的输出信号而变化。 每个延迟电路通过不同的延迟路径重新路由输入信号，以在反馈回路电路的操作期间基于相位检测器的输出信号产生延迟的输出信号。

公开(公告)号：US08098082B1

公开(公告)日：2012-01-17

申请号：US12954204

申请日：2010-11-24

申请人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

发明人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

IPC分类号： H01L25/00 ,  H03K19/177

CPC分类号： H03K19/017581 ,  H03K19/17744

摘要： Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.

摘要翻译： 用于实现可编程逻辑器件的高速多数据速率接口架构的方法和电路。 本发明将I / O引脚及其对应的寄存器分为独立的多数据速率I / O模块，每个I / O引脚具有至少一个专用于选通信号DQS的引脚和其他引脚用于DQ数据信号。 模块化架构便于引脚从一代PLD迁移到下一代。

公开(公告)号：US07884619B1

公开(公告)日：2011-02-08

申请号：US12566157

申请日：2009-09-24

申请人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Eric Choong-Yin Chang ,  Peter Boyle ,  Adam J. Wright

发明人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Eric Choong-Yin Chang ,  Peter Boyle ,  Adam J. Wright

IPC分类号： G01R35/00 ,  G01R23/175 ,  G08B23/00 ,  H03L7/00

CPC分类号： H03K5/135 ,  G01R31/3016 ,  G01R31/31725 ,  G01R31/318516 ,  H03K5/14 ,  H03K5/1504

摘要： Delay associated with each of two signals along respective transmission paths is accurately measured using a delay measurement circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated. Thus, the measured delay associated with each of the two signals is subject to the same fabrication-dependent attributes that affect the actual circuitry through which the two signals will be propagated during operation of the device. The skew between the two signals is quantified as the difference in the measured delays. Coarse and fine delay modules are defined within the transmission path of each of the two signals. Based on the measured skew between the two signals, the coarse and fine delay modules are appropriately set to compensate for the skew. The appropriately settings for the coarse and fine delay modules can be stored in non-volatile memory elements.

摘要翻译： 使用延迟测量电路精确测量与各传输路径中的两个信号中的每一个相关的延迟，该延迟测量电路在实际设备上制造，其中制造用于传播两个信号的电路。 因此，与两个信号中的每一个相关联的测量的延迟受到影响在设备操作期间两个信号将被传播的实际电路的相同制造相关属性。 两个信号之间的偏差被量化为测量延迟的差。 在两个信号中的每一个的传输路径内定义粗略和精细的延迟模块。 基于两个信号之间的测量偏差，粗调和精细延迟模块被适当地设置以补偿偏斜。 粗略和精细延迟模块的适当设置可以存储在非易失性存储器元件中。

公开(公告)号：US07859304B1

公开(公告)日：2010-12-28

申请号：US12329553

申请日：2008-12-06

申请人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

发明人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

IPC分类号： H01L25/00 ,  H03K19/177

CPC分类号： H03K19/017581 ,  H03K19/17744

摘要： Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.

摘要翻译： 用于实现可编程逻辑器件的高速多数据速率接口架构的方法和电路。 本发明将I / O引脚及其对应的寄存器分为独立的多数据速率I / O模块，每个I / O引脚具有至少一个专用于选通信号DQS的引脚和其他引脚用于DQ数据信号。 模块化架构便于引脚从一代PLD迁移到下一代。

公开(公告)号：US07825682B1

公开(公告)日：2010-11-02

申请号：US12147403

申请日：2008-06-26

申请人： Xiaobao Wang ,  Chiakang Sung ,  Khai Q. Nguyen ,  Sanjay K. Charagulla

发明人： Xiaobao Wang ,  Chiakang Sung ,  Khai Q. Nguyen ,  Sanjay K. Charagulla

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K19/0005 ,  H03K17/005 ,  H03K17/145 ,  H03K17/6871 ,  H03K17/6872 ,  H03K17/693

摘要： Techniques are provided for individually adjusting the on-chip termination impedance that is generated by input and output (IO) buffers in an input/output (IO) bank on an integrated circuit. The IO buffers in an IO bank can generate different on-chip termination impedances. And as a result, an IO bank can support more than one class of memory interfaces. An OCT calibration block generates a digital on-chip termination (OCT) calibration code. In some embodiments, circuitry in the IO banks can be configured to shift the OCT calibration code by one or more bits to adjust the series and/or parallel on-chip termination impedance in one or more IO buffers.

摘要翻译： 提供了用于单独调整由集成电路中的输入/输出（IO）组中的输入和输出（IO）缓冲器产生的片上终端阻抗的技术。 IO bank中的IO缓冲区可以产生不同的片上终端阻抗。 因此，IO bank可以支持多个类别的内存接口。 OCT校准块产生数字片上终端（OCT）校准码。 在一些实施例中，IO组中的电路可被配置为将OCT校准码移位一个或多个位以调整一个或多个IO缓冲器中的串联和/或并行片上终端阻抗。