公开(公告)号：US07592619B2

公开(公告)日：2009-09-22

申请号：US11622490

申请日：2007-01-12

Applicant: Pang-Yen Tsai ,  Liang-Gi Yao ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Shih-Chang Chen

Inventor： Pang-Yen Tsai ,  Liang-Gi Yao ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Shih-Chang Chen

IPC: H01L29/15

CPC classification number: C30B25/00 ,  C30B29/06 ,  C30B29/52 ,  Y10S438/933

Abstract: A method of forming an epitaxial layer of uniform thickness is provided to improve surface flatness. A substrate is first provided and a Si base layer is then formed on the substrate by epitaxy. A Si—Ge layer containing 5 to 10% germanium is formed on the Si base layer by epitaxy to normalize the overall thickness of the Si base layer and the Si—Ge layer containing 5 to 10% germanium.

Abstract translation: 提供了形成均匀厚度的外延层的方法以改善表面平坦度。 首先提供衬底，然后通过外延在衬底上形成Si基层。 通过外延在Si基底层上形成含有5〜10％锗的Si-Ge层，以使Si基层和含有5〜10％锗的Si-Ge层的整体厚度归一化。

公开(公告)号：US07521800B2

公开(公告)日：2009-04-21

申请号：US11752934

申请日：2007-05-24

Applicant: Chih-Chung Chu ,  Shih-Tsung Lin ,  Hsien-Chieh Lin

Inventor： Chih-Chung Chu ,  Shih-Tsung Lin ,  Hsien-Chieh Lin

IPC: H01L23/48

CPC classification number: H01L23/49816 ,  H01L23/498 ,  H01L2924/0002 ,  H05K1/113 ,  H05K3/108 ,  H05K3/243 ,  H05K3/3452 ,  H05K3/3457 ,  H05K3/4007 ,  H05K3/4644 ,  H05K2201/0367 ,  H05K2201/09563 ,  H05K2201/099 ,  H05K2203/0574 ,  H01L2924/00

Abstract: A solder pad structure includes a first metal layer disposed on an insulation layer, wherein the first metal layer is electrically connected with an underlying interconnection circuit layer through a conductive through hole disposed in the insulation layer. A solder resist layer having an opening exposing a central portion of the first metal layer is disposed on the insulating layer. A pillar-shaped second metal layer is disposed within the opening directly on the first metal layer. A solder ball filled into the opening is in contact with the pillar-shaped second metal layer.

Abstract translation: 焊盘结构包括设置在绝缘层上的第一金属层，其中第一金属层通过布置在绝缘层中的导电通孔与下层互连电路层电连接。 具有暴露第一金属层的中心部分的开口的阻焊层设置在绝缘层上。 柱形的第二金属层直接设置在第一金属层的开口内。 填充到开口中的焊球与柱状的第二金属层接触。

公开(公告)号：US20090073671A1

公开(公告)日：2009-03-19

申请号：US11961332

申请日：2007-12-20

Applicant: SHIH-CHIEH LIN

Inventor： SHIH-CHIEH LIN

IPC: H05K9/00

CPC classification number: H05K9/0026 ,  H04M1/14

Abstract: A housing combination includes a housing (51) and a shielding enclosure (55). The housing has a peripheral wall and a receiving hole (511). The peripheral wall surrounds the receiving hole configured for receiving a surface contact card. A guiding element (52) is positioned in at least one part of the peripheral wall of the receiving hole. The shielding enclosure is disposed at one side of the housing, one part of the shielding enclosure exposed from the receiving hole configured for supporting the surface contact card.

Abstract translation: 壳体组合包括壳体（51）和屏蔽罩（55）。 壳体具有周壁和容纳孔（511）。 周壁围绕配置用于接收表面接触卡的接收孔。 引导元件（52）定位在容纳孔的周壁的至少一部分中。 屏蔽壳体设置在壳体的一侧，屏蔽壳体的一部分从容纳孔露出，用于支撑表面接触卡。

公开(公告)号：US20090014521A1

公开(公告)日：2009-01-15

申请号：US11775992

申请日：2007-07-11

Applicant: CHI-TUNG CHANG ,  SHIH-MIN LAN ,  I-CHIEH LIN

Inventor： CHI-TUNG CHANG ,  SHIH-MIN LAN ,  I-CHIEH LIN

IPC: G06K7/06

CPC classification number: G06K7/0013

Abstract: A card reader that can enhance the efficiency of the application system is embedded in the application system. The application system has an external memory drive. The card reader includes at least one memory card connector, a flash memory, and a control unit. The memory card connector is used for being plugged with a memory card. The flash memory is driven and integrated by the external memory drive. The control unit is electrically connected with the memory card connector and the flash memory and is used for transmitting data between the memory card and the flash memory and the application system via the control unit. Thereby, the flash memory can be used as an extended memory of the application system. The total memory of the application system increases, and the efficiency of the application system is enhanced.

Abstract translation: 可以提高应用系统效率的读卡器嵌入在应用系统中。 应用系统具有外部存储器驱动器。 读卡器包括至少一个存储卡连接器，闪存和控制单元。 存储卡连接器用于插入存储卡。 闪存由外部存储器驱动并集成。 控制单元与存储卡连接器和闪速存储器电连接，并用于通过控制单元在存储卡与闪存和应用系统之间传输数据。 因此，闪存可以用作应用系统的扩展存储器。 应用系统的总内存增加，提高了应用系统的效率。

公开(公告)号：US20090000908A1

公开(公告)日：2009-01-01

申请号：US12218625

申请日：2008-07-15

Applicant: Michael D. Brain ,  Chun-Chieh Lin

Inventor： Michael D. Brain ,  Chun-Chieh Lin

IPC: B65G49/07 ,  G06F7/00

CPC classification number: B65G37/005 ,  B65G37/02 ,  B65G2201/0297 ,  H01L21/67276 ,  H01L21/67715 ,  H01L21/67769

Abstract: A system for buffering articles in transport is provided. The system comprises a buffer module configured to buffer articles and a computing system. The buffer module includes a first conveyor configured to transport the articles and a transference node configured to transfer the articles between the first conveyor and an external location. The computing system is configured to maintain an inventory list including a present location of each of the articles buffered by the buffer module. The computing system is further configured to control operation of the buffer module to transfer a selected article among the buffered articles to the external location.

Abstract translation: 提供了一种用于在运输中缓冲物品的系统。 该系统包括被配置为缓冲物品和计算系统的缓冲模块。 缓冲器模块包括构造成输送物品的第一传送器和被配置成在第一传送器和外部位置之间传送物品的传送节点。 计算系统被配置为维护包括由缓冲器模块缓冲的每个文章的当前位置的清单列表。 计算系统还被配置为控制缓冲器模块的操作以将缓冲的物品中的所选物品传送到外部位置。

公开(公告)号：US20080315398A1

公开(公告)日：2008-12-25

申请号：US11830822

申请日：2007-07-30

Applicant: Hsing-Lun Lo ,  Shih-Tsung Lin ,  Hsien-Chieh Lin ,  Kuo-Chun Chiang

Inventor： Hsing-Lun Lo ,  Shih-Tsung Lin ,  Hsien-Chieh Lin ,  Kuo-Chun Chiang

IPC: H01L23/48 ,  H01L23/10

CPC classification number: H01L24/82 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L2224/12105 ,  H01L2224/24227 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0206 ,  H05K1/183 ,  H05K1/185 ,  H05K3/4644 ,  H05K2201/09981 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2224/0401

Abstract: An embedded chip package includes a substrate having a dielectric interposer, a first metal foil on a first surface and a second metal foil on a second surface of the substrate, wherein the substrate has a cavity recessed into the first surface; a metal heatsink embedded within the cavity; a semiconductor die mounted on a flat bottom of the metal heatsink; a dielectric layer covering the first surface of the substrate; at least one built-up circuit trace layer on the dielectric layer; a solder resist layer on the built-up circuit trace layer and on the dielectric layer; a heat-dissipating metal layer on the second metal foil; and heat-dissipating plugs connecting the flat bottom of the metal heatsink and the heat-dissipating metal layer.

Abstract translation: 嵌入式芯片封装包括具有电介质插入件的基板，在第一表面上的第一金属箔和在基板的第二表面上的第二金属箔，其中所述基板具有凹入所述第一表面的空腔; 嵌入腔内的金属散热器; 安装在金属散热器的平坦底部的半导体管芯; 覆盖基板的第一表面的电介质层; 电介质层上的至少一个积聚电路迹线层; 在积层电路迹线层和电介质层上的阻焊层; 第二金属箔上的散热金属层; 以及连接金属散热器的平坦底部和散热金属层的散热塞。

公开(公告)号：US20080265256A1

公开(公告)日：2008-10-30

申请号：US11796369

申请日：2007-04-27

Applicant: Chun-Chieh Lin ,  Wei-Hua Hsu ,  Yu-En Percy Chang ,  Chung Li Chang ,  Chi-Feng Cheng ,  Win Hung ,  Kishimoto Ko

Inventor： Chun-Chieh Lin ,  Wei-Hua Hsu ,  Yu-En Percy Chang ,  Chung Li Chang ,  Chi-Feng Cheng ,  Win Hung ,  Kishimoto Ko

IPC: H01L29/94

CPC classification number: H01L29/665 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a SiGe region in the semiconductor substrate and adjacent the gate stack, wherein the SiGe region has a first atomic percentage of germanium to germanium and silicon; and a silicide region over the SiGe region. The silicide region has a second atomic percentage of germanium to germanium and silicon. The second atomic percentage is substantially lower than the first atomic percentage.

Abstract translation: 提供半导体结构及其形成方法。 半导体结构包括半导体衬底; 半导体衬底上的栅极堆叠; SiGe区域，其中SiGe区域具有锗到锗和硅的第一原子百分比; 以及SiGe区域上的硅化物区域。 硅化物区域具有锗与锗和硅的第二原子百分比。 第二原子百分比基本上低于第一原子百分数。

公开(公告)号：US07443230B2

公开(公告)日：2008-10-28

申请号：US11463597

申请日：2006-08-10

Applicant: Chung-Zen Chen ,  Chung-Shan Kuo ,  Yang-Chieh Lin

Inventor： Chung-Zen Chen ,  Chung-Shan Kuo ,  Yang-Chieh Lin

IPC: G05F1/10

CPC classification number: H02M3/07

Abstract: A charge pump circuit including a plurality of controlled charge pumps (CPs), a plurality of uncontrolled CPs, a plurality of control units, and an output unit is provided. Each controlled CP determines whether to provide charges to a node by a control signal, and each uncontrolled CP constantly provides charges to the node. The higher the node voltage at the node is, the more the controlled CPs not providing charge to the node are, so as to suppress the voltage of the node. In addition, the output unit regulates and outputs an output voltage according to the node voltage by the negative feedback.

Abstract translation: 提供了包括多个受控电荷泵（CP），多个不受控制的CP，多个控制单元和输出单元的电荷泵电路。 每个受控CP确定是否通过控制信号向节点提供费用，并且每个不受控制的CP不断向节点提供费用。 节点处的节点电压越高，对节点不提供电荷的受控CP越多，以抑制节点的电压。 此外，输出单元通过负反馈调节并输出根据节点电压的输出电压。

公开(公告)号：US20080249949A1

公开(公告)日：2008-10-09

申请号：US11733163

申请日：2007-04-09

Applicant: Chia-Chin Wang ,  Yung-Chieh Lin ,  Ming-Tsung Lin

Inventor： Chia-Chin Wang ,  Yung-Chieh Lin ,  Ming-Tsung Lin

IPC: H04L9/30

CPC classification number: H04L67/104 ,  G06Q20/401 ,  H04L9/08 ,  H04L67/108 ,  H04L67/1082 ,  H04L2209/56

Abstract: A data exchange method between a first peer system having a requested data chunk and a second peer system having a credit includes: exchanging the credit of the second peer system for the requested data chunk of the first peer system; and using the credit received by the first peer system to exchange for a future data chunk from the second peer system at a later time.

Abstract translation: 具有所请求的数据块的第一对等系统和具有信用的第二对等系统之间的数据交换方法包括：为所述第一对等系统的所请求的数据块交换所述第二对等系统的信用; 并且使用由第一对等系统接收的信用以在稍后时间从第二对等系统交换未来的数据块。

公开(公告)号：US07423347B2

公开(公告)日：2008-09-09

申请号：US11334849

申请日：2006-01-19

Applicant: Chung-Hsien Chen ,  Chun-Chieh Lin ,  Minghsing Tsai ,  Shau-Lin Shue

Inventor： Chung-Hsien Chen ,  Chun-Chieh Lin ,  Minghsing Tsai ,  Shau-Lin Shue

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/53238 ,  H01L21/2885 ,  H01L21/76877 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor interconnect structure having reduced hillock formation and a method for forming the same are provided. The semiconductor interconnect structure includes a conductor formed in a dielectric layer. The conductor includes at least three sub-layers, wherein the ratio of the impurity concentrations in neighboring sub-layers is preferably greater than about two.

Abstract translation: 提供了具有减小的小丘形成的半导体互连结构及其形成方法。 半导体互连结构包括形成在电介质层中的导体。 导体包括至少三个子层，其中相邻子层中杂质浓度的比优选大于约2。