公开(公告)号：US20160018079A1

公开(公告)日：2016-01-21

申请号：US14870382

申请日：2015-09-30

Applicant: CHIEN-TING LIN

Inventor： CHIEN-TING LIN

IPC: F21V7/18 ,  F21V1/06

CPC classification number: G03B15/06 ,  A45B2019/001 ,  F21V1/06

Abstract: A lighting assembly used in photographing or video recording has a light cover with X-shaped structure, which includes a main body and two elastic supporting rods. The main body has a light holder fitting opening at a center thereof. The two elastic supporting rods are fixed along four edges of the main body in such a way that they cross each other at the center thereof at the light holder fitting opening. The light cover can be folded from a tent-like form to an easy-to-carry flattened form.

Abstract translation: 用于拍摄或录像的照明组件具有X形结构的遮光罩，其包括主体和两个弹性支撑杆。 主体在其中心具有灯座配件开口。 两个弹性支撑杆沿着主体的四个边缘固定，使得它们在灯架配件开口处的中心彼此交叉。 灯罩可以从帐篷状折叠成易于携带的扁平形式。

公开(公告)号：US09105623B2

公开(公告)日：2015-08-11

申请号：US13480499

申请日：2012-05-25

Applicant: Wen-Tai Chiang ,  Chien-Ting Lin

Inventor： Wen-Tai Chiang ,  Chien-Ting Lin

IPC: H01L21/8238 ,  H01L29/49 ,  H01L27/088 ,  H01L21/28 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/823842 ,  H01L27/088 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659

Abstract: A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench, forming a first work function metal layer and an etch stop layer in the first gate trench and the second gate trench, forming a metal layer having a material the same with the first work function metal layer in the second gate trench, and forming a filling metal layer in the first gate trench and the second gate trench to form a second work function metal layer in the first gate trench.

Abstract translation: 具有金属栅极的半导体器件的制造方法包括：提供具有第一半导体器件和形成在其上的第二半导体器件的衬底，所述第一半导体器件具有第一栅极沟槽，所述第二半导体器件具有第二栅极沟槽，形成第一工件 在第一栅极沟槽和第二栅极沟槽中形成功能金属层和蚀刻停止层，形成具有与第二栅极沟槽中的第一功函数金属层相同的材料的金属层，并且在第一栅极沟槽和第二栅极沟槽中形成填充金属层 栅极沟槽和第二栅极沟槽，以在第一栅极沟槽中形成第二功函数金属层。

公开(公告)号：US20150176822A1

公开(公告)日：2015-06-25

申请号：US14139795

申请日：2013-12-23

Applicant: CHIEN-TING LIN

Inventor： CHIEN-TING LIN

IPC: F21V21/088

CPC classification number: F21V21/088 ,  F21V7/18 ,  G03B15/06

Abstract: The present invention provides a light reflector clamp for mounting a light reflector with a rod member. The light reflector clamp of the present invention includes a central member, a groove and a turning clamp set. A rod member clamping seat is disposed on the central member, and a mounting portion is disposed at an opening of the rod member clamping seat. The groove is disposed on the central member, and the turning clamp set is disposed on the central member next to the groove. At least one of the light reflector clamp is mounted on the rod member via the rod member clamping seat. An edge of the light reflector is fitted in the groove, and at least one of the turning clamp set is utilized to fix the edge of the light reflector with the at least one light reflector clamp.

Abstract translation: 本发明提供了一种用于安装具有杆构件的光反射器的光反射器夹具。 本发明的光反射器夹具包括中心构件，凹槽和转动夹具组。 杆构件夹持座设置在中心构件上，并且安装部设置在杆构件夹持座的开口处。 凹槽设置在中心构件上，并且转动夹具组设置在靠近凹槽的中心构件上。 光反射器夹具中的至少一个通过杆构件夹持座安装在杆构件上。 光反射器的边缘装配在凹槽中，并且利用至少一个转动夹具将光反射器的边缘与至少一个光反射器夹具固定。

公开(公告)号：US08691651B2

公开(公告)日：2014-04-08

申请号：US13218438

申请日：2011-08-25

Applicant: Sheng-Huei Dai ,  Rai-Min Huang ,  Chen-Hua Tsai ,  Shih-Hung Tsai ,  Chien-Ting Lin

Inventor： Sheng-Huei Dai ,  Rai-Min Huang ,  Chen-Hua Tsai ,  Shih-Hung Tsai ,  Chien-Ting Lin

IPC: H01L21/8234 ,  H01L21/336

CPC classification number: H01L29/7851 ,  H01L21/845 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/66795

Abstract: A method of forming a Non-planar FET is provided. A substrate is provided. An active region and a peripheral region are defined on the substrate. A plurality of VSTI is formed in the active region of the substrate. A part of each VSTI is removed to expose a part of sidewall of the substrate. Then, a conductor layer is formed on the substrate which is then patterned to form a planar FET gate in the peripheral region and a Non-planar FET gate in the active region simultaneously. Last, a source/drain region is formed on two sides of the Non-planar FET gate.

Abstract translation: 提供一种形成非平面FET的方法。 提供基板。 在衬底上限定有源区和周边区。 在基板的有源区域中形成多个VSTI。 去除每个VSTI的一部分以露出衬底的侧壁的一部分。 然后，在衬底上形成导体层，然后将其图案化以在外围区域中形成平面FET栅极，并且在有源区域中同时形成非平面FET栅极。 最后，源极/漏极区域形成在非平面FET栅极的两侧。

公开(公告)号：US20130313648A1

公开(公告)日：2013-11-28

申请号：US13480499

申请日：2012-05-25

Applicant: Wen-Tai Chiang ,  Chien-Ting Lin

Inventor： Wen-Tai Chiang ,  Chien-Ting Lin

IPC: H01L21/28 ,  H01L27/088

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/823842 ,  H01L27/088 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659

Abstract: A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench, forming a first work function metal layer and an etch stop layer in the first gate trench and the second gate trench, forming a metal layer having a material the same with the first work function metal layer in the second gate trench, and forming a filling metal layer in the first gate trench and the second gate trench to form a second work function metal layer in the first gate trench.

Abstract translation: 一种具有金属栅极的半导体器件的制造方法，包括提供具有第一半导体器件和形成在其上的第二半导体器件的衬底，所述第一半导体器件具有第一栅极沟槽，所述第二半导体器件具有第二栅极沟槽，形成第一工件 在第一栅极沟槽和第二栅极沟槽中形成功能金属层和蚀刻停止层，形成具有与第二栅极沟槽中的第一功函数金属层相同的材料的金属层，并且在第一栅极沟槽和第二栅极沟槽中形成填充金属层 栅极沟槽和第二栅极沟槽，以在第一栅极沟槽中形成第二功函数金属层。

公开(公告)号：US08470714B1

公开(公告)日：2013-06-25

申请号：US13477079

申请日：2012-05-22

Applicant: Shih-Hung Tsai ,  Ssu-I Fu ,  Chien-Liang Lin ,  Ying-Tsung Chen ,  Ted Ming-Lang Guo ,  Chin-Cheng Chien ,  Chien-Ting Lin ,  Wen-Tai Chiang

Inventor： Shih-Hung Tsai ,  Ssu-I Fu ,  Chien-Liang Lin ,  Ying-Tsung Chen ,  Ted Ming-Lang Guo ,  Chin-Cheng Chien ,  Chien-Ting Lin ,  Wen-Tai Chiang

IPC: H01L21/311

CPC classification number: H01L29/7854 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/66795

Abstract: A method of forming fin structure in integrated circuit comprising the steps of forming a plurality of fin structures on a substrate, covering an insulating layer on said substrate, performing a planarization process to expose mask layers, performing a wet etching process to etch said insulating layer, thereby exposing a part of the sidewall of said mask layer, removing said mask layer, and performing a dry etching process to remove pad layer and a part of said insulating layer, thereby exposing the top surface and a part of sidewall of said fin structures.

Abstract translation: 一种在集成电路中形成鳍结构的方法，包括以下步骤：在衬底上形成多个翅片结构，覆盖所述衬底上的绝缘层，执行平坦化处理以曝光掩模层，执行湿蚀刻工艺以蚀刻所述绝缘层 从而暴露所述掩模层的侧壁的一部分，去除所述掩模层，并进行干蚀刻工艺以去除衬垫层和所述绝缘层的一部分，从而暴露所述鳍结构的顶表面和侧壁的一部分 。

公开(公告)号：US20130126972A1

公开(公告)日：2013-05-23

申请号：US13304086

申请日：2011-11-23

Applicant: Chang-Tzu Wang ,  Mei-Ling Chao ,  Chien-Ting Lin

Inventor： Chang-Tzu Wang ,  Mei-Ling Chao ,  Chien-Ting Lin

IPC: H01L27/12 ,  H01L21/336

CPC classification number: H01L29/66795 ,  H01L21/26513 ,  H01L21/823821 ,  H01L27/0924

Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate of a first conductivity type, a fin, a gate, source and drain regions of a second conductivity type, and a first doped region of the second conductivity type. A plurality of isolation structures is formed on the substrate. The fin is disposed on the substrate between two adjacent isolation structures. The gate is disposed on the isolation structures and covers a portion of the fin, wherein the portion of the fin covered by the gate is of the first conductivity type. The source and drain regions is configured in the fin at respective sides of the gate. The first doped region is configured in the fin underlying the source and drain regions and adjoining the substrate. The first doped region has an impurity concentration lower than that of the source and drain regions.

Abstract translation: 提供了一种半导体器件及其制造方法。 半导体器件包括具有第二导电类型的第一导电类型，鳍状物，栅极，源极和漏极区域以及第二导电类型的第一掺杂区域的衬底。 在基板上形成多个隔离结构。 翅片设置在两个相邻隔离结构之间的基板上。 栅极设置在隔离结构上并覆盖翅片的一部分，其中由栅极覆盖的鳍的部分是第一导电类型。 源极和漏极区域在栅极的相应侧配置在鳍片中。 第一掺杂区域配置在源极和漏极区域下方的鳍片中，并与衬底相邻。 第一掺杂区的杂质浓度低于源区和漏区。

公开(公告)号：US20130056827A1

公开(公告)日：2013-03-07

申请号：US13224344

申请日：2011-09-02

Applicant: Shih-Hung Tsai ,  Chien-Ting Lin ,  Chin-Cheng Chien ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Teng-Chun Tsai ,  Chun-Yuan Wu

Inventor： Shih-Hung Tsai ,  Chien-Ting Lin ,  Chin-Cheng Chien ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Teng-Chun Tsai ,  Chun-Yuan Wu

IPC: H01L21/84 ,  H01L27/12 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A non-planar semiconductor structure includes a substrate, at least two fin-shaped structures, at least an isolation structure, and a plurality of epitaxial layers. The fin-shaped structures are located on the substrate. The isolation structure is located between the fin-shaped structures, and the isolation structure has a nitrogen-containing layer. The epitaxial layers respectively cover a part of the fin-shaped structures and are located on the nitrogen-containing layer. A non-planar semiconductor process is also provided for forming the semiconductor structure.

Abstract translation: 非平面半导体结构包括衬底，至少两个鳍状结构，至少一个隔离结构和多个外延层。 鳍状结构位于基底上。 隔离结构位于鳍状结构之间，隔离结构具有含氮层。 外延层分别覆盖了鳍状结构的一部分并且位于含氮层上。 还提供了用于形成半导体结构的非平面半导体工艺。

公开(公告)号：US20120313178A1

公开(公告)日：2012-12-13

申请号：US13158479

申请日：2011-06-13

Applicant: Po-Jui Liao ,  Tsung-Lung Tsai ,  Chien-Ting Lin ,  Shao-Hua Hsu ,  Yeng-Peng Wang ,  Chun-Hsien Lin ,  Chan-Lon Yang ,  Guang-Yaw Hwang ,  Shin-Chi Chen ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Chia-Wen Liang

Inventor： Po-Jui Liao ,  Tsung-Lung Tsai ,  Chien-Ting Lin ,  Shao-Hua Hsu ,  Yeng-Peng Wang ,  Chun-Hsien Lin ,  Chan-Lon Yang ,  Guang-Yaw Hwang ,  Shin-Chi Chen ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Chia-Wen Liang

IPC: H01L21/3205 ,  H01L29/78

CPC classification number: H01L29/78 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/66545

Abstract: A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench formed therein, forming a first work function metal layer in the first gate trench, forming a sacrificial masking layer in the first gate trench, removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer, removing the exposed first function metal layer to form a U-shaped work function metal layer in the first gate trench, and removing the sacrificial masking layer. The first transistor includes a first conductivity type and the second transistor includes a second conductivity type. The first conductivity type and the second conductivity type are complementary.

Abstract translation: 一种制造具有金属栅极的半导体器件的方法包括：提供具有形成在其上的第一晶体管和第二晶体管的衬底，所述第一晶体管具有形成在其中的第一栅极沟槽，在所述第一栅极沟槽中形成第一功函数金属层， 在第一栅极沟槽中的牺牲掩模层，去除牺牲掩模层的一部分以暴露第一功函数金属层的一部分，去除暴露的第一功能金属层，以在第一栅极沟槽中的第一栅极沟槽中形成U形功函数金属层 栅极沟槽，以及去除牺牲掩模层。 第一晶体管包括第一导电类型，第二晶体管包括第二导电类型。 第一导电类型和第二导电类型是互补的。

公开(公告)号：US08198151B2

公开(公告)日：2012-06-12

申请号：US12890725

申请日：2010-09-27

Applicant: Chien-Ting Lin ,  Che-Hua Hsu ,  Li-Wei Cheng

Inventor： Chien-Ting Lin ,  Che-Hua Hsu ,  Li-Wei Cheng

IPC: H01L21/8238

CPC classification number: H01L21/28123 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: A method of fabricating a metal gate structure is provided. The method includes providing a semiconductor substrate with a planarized polysilicon material; patterned the planarized polysilicon material to form at least a first gate and a second gate, wherein the first gate is located on the active region and the second gate at least partially overlaps with the isolation region; forming an inter-layer dielectric material covering the gates; planarizing the inter-layer dielectric material until exposing the gates and forming an inter layer-dielectric layer; performing an etching process to remove the gates to form a first recess and a second recess within the inter-layer dielectric layer; forming a gate dielectric material on a surface of each of the recesses; forming at least a metal material within the recesses; and performing a planarization process.

Abstract translation: 提供一种制造金属栅极结构的方法。 该方法包括：提供具有平坦化多晶硅材料的半导体衬底; 将平坦化的多晶硅材料图案化以形成至少第一栅极和第二栅极，其中第一栅极位于有源区上，而第二栅极至少部分地与隔离区重叠; 形成覆盖所述栅极的层间电介质材料; 平面化层间电介质材料，直到露出栅极并形成层间介电层; 执行蚀刻工艺以移除所述栅极以在所述层间电介质层内形成第一凹部和第二凹槽; 在每个所述凹部的表面上形成栅极电介质材料; 在所述凹部内形成至少一种金属材料; 并执行平面化处理。