公开(公告)号：US08441072B2

公开(公告)日：2013-05-14

申请号：US13224344

申请日：2011-09-02

申请人： Shih-Hung Tsai ,  Chien-Ting Lin ,  Chin-Cheng Chien ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Teng-Chun Tsai ,  Chun-Yuan Wu

发明人： Shih-Hung Tsai ,  Chien-Ting Lin ,  Chin-Cheng Chien ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Teng-Chun Tsai ,  Chun-Yuan Wu

IPC分类号： H01L27/12

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A non-planar semiconductor structure includes a substrate, at least two fin-shaped structures, at least an isolation structure, and a plurality of epitaxial layers. The fin-shaped structures are located on the substrate. The isolation structure is located between the fin-shaped structures, and the isolation structure has a nitrogen-containing layer. The epitaxial layers respectively cover a part of the fin-shaped structures and are located on the nitrogen-containing layer. A non-planar semiconductor process is also provided for forming the semiconductor structure.

摘要翻译： 非平面半导体结构包括衬底，至少两个鳍状结构，至少一个隔离结构和多个外延层。 鳍状结构位于基底上。 隔离结构位于鳍状结构之间，隔离结构具有含氮层。 外延层分别覆盖了鳍状结构的一部分并且位于含氮层上。 还提供了用于形成半导体结构的非平面半导体工艺。

公开(公告)号：US20130056827A1

公开(公告)日：2013-03-07

申请号：US13224344

申请日：2011-09-02

申请人： Shih-Hung Tsai ,  Chien-Ting Lin ,  Chin-Cheng Chien ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Teng-Chun Tsai ,  Chun-Yuan Wu

发明人： Shih-Hung Tsai ,  Chien-Ting Lin ,  Chin-Cheng Chien ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Teng-Chun Tsai ,  Chun-Yuan Wu

IPC分类号： H01L21/84 ,  H01L27/12 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A non-planar semiconductor structure includes a substrate, at least two fin-shaped structures, at least an isolation structure, and a plurality of epitaxial layers. The fin-shaped structures are located on the substrate. The isolation structure is located between the fin-shaped structures, and the isolation structure has a nitrogen-containing layer. The epitaxial layers respectively cover a part of the fin-shaped structures and are located on the nitrogen-containing layer. A non-planar semiconductor process is also provided for forming the semiconductor structure.

摘要翻译： 非平面半导体结构包括衬底，至少两个鳍状结构，至少一个隔离结构和多个外延层。 鳍状结构位于基底上。 隔离结构位于鳍状结构之间，隔离结构具有含氮层。 外延层分别覆盖了鳍状结构的一部分并且位于含氮层上。 还提供了用于形成半导体结构的非平面半导体工艺。

公开(公告)号：US08609529B2

公开(公告)日：2013-12-17

申请号：US13363390

申请日：2012-02-01

申请人： Chin-Fu Lin ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Teng-Chun Tsai ,  Chin-Cheng Chien

发明人： Chin-Fu Lin ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Teng-Chun Tsai ,  Chin-Cheng Chien

IPC分类号： H01L21/4763

CPC分类号： H01L21/3085 ,  H01L21/3086 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a through silicon via (TSV) structure, in which, a patterned mask is formed on a substrate, the patterned mask has an opening, a spacer-shaped structure is formed on a sidewall of the opening, and a via hole having a relatively enlarged opening is formed by etching the spacer-shaped structure and the substrate through the opening after the spacer-shaped structure is formed. A TSV structure, in which, a via hole has an opening portion and a body portion, the opening portion is a relatively enlarged opening and has a tapered shape having an opening size of an upper portion greater than an opening size of a lower portion.

摘要翻译： 一种制造贯穿硅通孔（TSV）结构的方法，其中在基板上形成图案化掩模，所述图案化掩模具有开口，在所述开口的侧壁上形成间隔物结构，并且所述通孔 通过在形成间隔物结构之后通过开口蚀刻间隔物结构和基底而形成具有相对扩大的开口。 TSV结构，其中通孔具有开口部分和主体部分，所述开口部分是相对扩大的开口，并且具有开口尺寸大于下部开口尺寸的上部开口尺寸的锥形形状。

公开(公告)号：US20130207122A1

公开(公告)日：2013-08-15

申请号：US13370231

申请日：2012-02-09

申请人： Chin-Fu Lin ,  Chin-Cheng Chien ,  Chun-Yuan Wu ,  Teng-Chun Tsai ,  Chih-Chien Liu

发明人： Chin-Fu Lin ,  Chin-Cheng Chien ,  Chun-Yuan Wu ,  Teng-Chun Tsai ,  Chih-Chien Liu

IPC分类号： H01L21/764 ,  H01L29/24

CPC分类号： H01L29/785 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3115 ,  H01L21/3141 ,  H01L21/3185 ,  H01L21/764 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L27/10879 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795

摘要： A method for fabricating FinFETs is described. A semiconductor substrate is patterned to form odd fins. Spacers are formed on the substrate and on the sidewalls of the odd fins, wherein each spacer has a substantially vertical sidewall. Even fins are then formed on the substrate between the spacers. A semiconductor structure for forming FinFETs is also described, which is fabricated using the above method.

摘要翻译： 描述了制造FinFET的方法。 图案化半导体衬底以形成奇数鳍片。 间隔件形成在基底上和奇数翅片的侧壁上，其中每个间隔件具有基本垂直的侧壁。 然后在间隔件之间的基板上均匀形成翅片。 还描述了用于形成FinFET的半导体结构，其使用上述方法制造。

公开(公告)号：US20120319198A1

公开(公告)日：2012-12-20

申请号：US13161503

申请日：2011-06-16

申请人： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Teng-Chun Tsai

发明人： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Teng-Chun Tsai

IPC分类号： H01L29/78 ,  H01L21/3205

CPC分类号： H01L21/28158 ,  H01L21/28114 ,  H01L21/28185 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/49 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66545

摘要： A semiconductor device including a substrate, a spacer and a high-k dielectric layer having a U-shape profile is provided. The spacer located on the substrate surrounds and defines a trench. The high-k dielectric layer having a U-shape profile is located in the trench, and the high-k dielectric layer having a U-shape profile exposes an upper portion of the sidewalls of the trench.

摘要翻译： 提供了包括基板，间隔物和具有U形轮廓的高k电介质层的半导体器件。 位于基板上的间隔件围绕并限定沟槽。 具有U形轮廓的高k电介质层位于沟槽中，并且具有U形轮廓的高k电介质层露出沟槽的侧壁的上部。

公开(公告)号：US20120248507A1

公开(公告)日：2012-10-04

申请号：US13072795

申请日：2011-03-28

申请人： Chih-Chien Liu ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Teng-Chun Tsai ,  Chin-Cheng Chien

发明人： Chih-Chien Liu ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Teng-Chun Tsai ,  Chin-Cheng Chien

IPC分类号： H01L29/772 ,  H01L21/28

CPC分类号： H01L29/517 ,  H01L21/28185 ,  H01L29/513 ,  H01L29/66545

摘要： A manufacturing method of a metal gate structure includes providing a substrate having at least a first metal oxide layer formed thereon, and transferring the surface of the first metal oxide layer into a second metal oxide layer. The first metal oxide layer includes a metal oxide (M1Ox) of a first metal (M1) and the second metal oxide layer includes a metal oxide ((M1M2Oy) of the first metal and a second metal (M2).

摘要翻译： 金属栅极结构的制造方法包括提供具有形成在其上的至少第一金属氧化物层的基板，并将第一金属氧化物层的表面转移到第二金属氧化物层中。 第一金属氧化物层包括第一金属（M1）的金属氧化物（M1Ox），第二金属氧化物层包括第一金属的金属氧化物（（M1M2Oy））和第二金属（M2）。

公开(公告)号：US09184100B2

公开(公告)日：2015-11-10

申请号：US13206533

申请日：2011-08-10

申请人： Teng-Chun Tsai ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Cheng Chien ,  Chin-Fu Lin

发明人： Teng-Chun Tsai ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Cheng Chien ,  Chin-Fu Lin

IPC分类号： H01L27/092 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/10

CPC分类号： H01L21/845 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/165

摘要： A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate.

摘要翻译： 半导体器件包括半导体衬底，至少第一鳍结构，至少第二鳍结构，第一栅极，第二栅极，第一源极/漏极区域和第二源极/漏极区域。 半导体衬底至少具有第一有源区以配置第一鳍结构和至少第二有源区以配置第二鳍结构。 与第一/第二栅极部分重叠的第一/第二鳍结构具有第一/第二应力，第一应力和第二应力彼此不同。 第一/第二源极/漏极区域设置在第一/第二栅极的两侧的第一/第二鳍结构中。

公开(公告)号：US08822336B2

公开(公告)日：2014-09-02

申请号：US13161849

申请日：2011-06-16

申请人： Teng-Chun Tsai ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Chin-Cheng Chien

发明人： Teng-Chun Tsai ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Chin-Cheng Chien

IPC分类号： H01L21/283

CPC分类号： H01L21/76898 ,  H01L21/76883

摘要： A through-silicon via forming method includes the following steps. Firstly, a semiconductor substrate is provided. Then, a through-silicon via conductor is formed in the semiconductor substrate, and a topside of the through-silicon via conductor is allowed to be at the same level as a surface of the semiconductor substrate. Afterwards, a portion of the through-silicon via conductor is removed, and the topside of the through-silicon via conductor is allowed to be at a level lower than the surface of the semiconductor substrate, so that a recess is formed over the through-silicon via conductor.

摘要翻译： 通硅通孔形成方法包括以下步骤。 首先，提供半导体衬底。 然后，在半导体衬底中形成贯通硅通孔导体，并且使贯通硅通孔导体的上侧与半导体衬底的表面处于相同的水平。 然后，去除一部分通硅导通导体，使贯通硅通孔导体的顶面位于比半导体衬底的表面低的水平面上， 硅通孔导体。

公开(公告)号：US20130078778A1

公开(公告)日：2013-03-28

申请号：US13243485

申请日：2011-09-23

申请人： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Teng-Chun Tsai

发明人： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Teng-Chun Tsai

IPC分类号： H01L21/336

CPC分类号： H01L29/66795

摘要： A semiconductor process is described as follows. A plurality of dummy patterns is formed on a substrate. A mask material layer is conformally formed on the substrate, so as to cover the dummy patterns. The mask material layer has an etching rate different from that of the dummy patterns. A portion of the mask material layer is removed, so as to form a mask layer on respective sidewalls of each dummy pattern. An upper surface of the mask layer and an upper surface of each dummy pattern are substantially coplanar. The dummy patterns are removed. A portion of the substrate is removed using the mask layer as a mask, so as to form a plurality of fin structures and a plurality of trenches alternately arranged in the substrate. The mask layer is removed.

摘要翻译： 半导体工艺描述如下。 在基板上形成多个虚设图案。 在基板上共形形成掩模材料层，以覆盖虚设图案。 掩模材料层具有与虚拟图案不同的蚀刻速率。 除去掩模材料层的一部分，以便在每个虚设图案的各个侧壁上形成掩模层。 掩模层的上表面和每个虚拟图案的上表面基本上共面。 虚拟图案被去除。 使用掩模层作为掩模去除衬底的一部分，以便形成多个翅片结构和交替布置在衬底中的多个沟槽。 去除掩模层。

公开(公告)号：US20130037886A1

公开(公告)日：2013-02-14

申请号：US13206533

申请日：2011-08-10

申请人： Teng-Chun Tsai ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Cheng Chien ,  Chin-Fu Lin

发明人： Teng-Chun Tsai ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Cheng Chien ,  Chin-Fu Lin

IPC分类号： H01L27/092 ,  H01L21/782 ,  H01L27/12 ,  H01L21/8238

CPC分类号： H01L21/845 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/165

摘要： A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate.

摘要翻译： 半导体器件包括半导体衬底，至少第一鳍结构，至少第二鳍结构，第一栅极，第二栅极，第一源极/漏极区域和第二源极/漏极区域。 半导体衬底至少具有第一有源区以配置第一鳍结构和至少第二有源区以配置第二鳍结构。 与第一/第二栅极部分重叠的第一/第二鳍结构具有第一/第二应力，第一应力和第二应力彼此不同。 第一/第二源极/漏极区域设置在第一/第二栅极的两侧的第一/第二鳍结构中。