公开(公告)号：US20200035670A1

公开(公告)日：2020-01-30

申请号：US16153829

申请日：2018-10-08

Applicant: Faraday Technology Corp.

Inventor： Chia-Ku Tsai ,  Chi-Sheng Liao ,  Jeng-Huang Wu

IPC: H01L27/02 ,  H02H9/04

Abstract: A electrostatic discharge (ESD) protection apparatus for an integrated circuit (IC) is provided. A first electrostatic current rail and a second electrostatic current rail of the ESD protection apparatus do not directly connected to any bonding pad of the IC. The ESD protection apparatus further includes a clamp circuit and four ESD protection circuits. The clamp circuit is coupled between the first electrostatic current rail and the second electrostatic current rail. A first ESD protection circuit is coupled between the first electrostatic current rail and a signal pad of the IC. A second ESD protection circuit is coupled between the signal pad and the second electrostatic current rail. A third ESD protection circuit is coupled between a first power rail and the second electrostatic current rail. A fourth ESD protection circuit is coupled between the second electrostatic current rail and a second power rail.

公开(公告)号：US10523470B1

公开(公告)日：2019-12-31

申请号：US16286511

申请日：2019-02-26

Applicant: Faraday Technology Corp.

Inventor： Chia-Lin Hu

IPC: H04M7/12 ,  H04L25/02 ,  H03F3/45 ,  H03F3/68 ,  H04L25/06

Abstract: An apparatus for performing baseline wander correction is provided. The apparatus may include: a plurality of filters, a common mode voltage generator, and a compensation circuit. The plurality of filters may filter a set of input signals to generate a set of differential signals, the common mode voltage generator may generate a common mode voltage between the set of differential signals, and the compensation circuit may perform compensation related to baseline wander correction on the set of differential signals. Multiple current paths of the compensation circuit are associated with each other. Through a first current path and a second current path within the current paths, the compensation circuit may perform charge or discharge control on a first capacitor and a second capacitor within the plurality of filters to dynamically adjust compensation amounts of the compensation, to reduce or eliminate a baseline wander effect of the set of differential signals.

公开(公告)号：US20190278912A1

公开(公告)日：2019-09-12

申请号：US16011650

申请日：2018-06-19

Applicant: Faraday Technology Corp.

Inventor： Chun-Yuan Lai ,  Chen-Chun Huang

IPC: G06F21/57 ,  G06F8/65 ,  G06F8/30 ,  G06F8/71 ,  G06F21/73 ,  G06F21/76 ,  G06F21/60

Abstract: A method and apparatus for performing firmware programming on a microcontroller chip and the associated microcontroller chip are provided. The method includes: utilizing an integrated circuit (IC) programmer to generate a seed file including characteristic information of the IC programmer; utilizing an encoder to encrypt original data representing a program code at least according to the characteristic information, to generate an encryption version of the original data; utilizing the IC programmer to decrypt the encryption version of the original data according to the characteristic information, to generate the original data utilizing the IC programmer to encrypt the original data at least according to predetermined information, to generate another encryption version of the original data; utilizing the microcontroller chip to decrypt the other encryption version at least according to predetermined information stored in the microcontroller chip to generate the original data, and write the original data into a non-volatile (NV) memory.

公开(公告)号：US20180351351A1

公开(公告)日：2018-12-06

申请号：US15694847

申请日：2017-09-03

Applicant: Faraday Technology Corp.

Inventor： Chia-Ku Tsai

IPC: H02H9/04

Abstract: An electrostatic discharge (ESD) protection apparatus includes: an ESD circuit, arranged to perform ESD protection, wherein the ESD circuit includes a first Field Effect Transistor (FET) arranged to release ESD energy; a detection circuit, arranged to perform detection to control the ESD protection apparatus to selectively operate in one of a normal mode and a discharge mode; and a logic circuit, arranged to withstand any oscillation due to resistance-inductance-capacitance (RLC) characteristics of the detection circuit. In the detection circuit, different subsets of a plurality of resistors are respectively combined with a portion of a first serial connection circuit, an entirety of the first serial connection circuit, and a second FET to form different serial connection circuits, to configure the second FET to approach a state of being completely turned off in the normal mode.

公开(公告)号：US09965430B2

公开(公告)日：2018-05-08

申请号：US15001196

申请日：2016-01-19

Applicant: Faraday Technology Corp.

Inventor： Yuan-Min Hu ,  Yin-Fu Lin ,  Shan-Chih Wen

IPC: G06F13/00 ,  G06F13/40

CPC classification number: G06F13/4068

Abstract: An integrated circuit and an operation method of a SERDES PHY layer circuit thereof are provided. When the SERDES PHY layer circuit is in a calibration preparation state and a signal of a first calibration input pin is an enable state, or when the SERDES PHY layer circuit is in the calibration preparation state, and signals of first and second calibration input pins are in the enable state, the SERDES PHY layer circuit enters a calibration state (using a reference resistor for current calibration). After the current calibration is completed, the SERDES PHY layer circuit enters a calibration completion state (without using the reference resistor and connecting the first calibration input pin to the first calibration output pin). The SERDES PHY layer circuit sets the signal of the first calibration output pin to a disable state when the SERDES PHY layer circuit is not in the calibration completion state.

公开(公告)号：US20180109227A1

公开(公告)日：2018-04-19

申请号：US15385871

申请日：2016-12-21

Applicant: Faraday Technology Corp.

Inventor： Chih-Huang Lin

IPC: H03F1/30 ,  H03G3/30 ,  H03F3/45

CPC classification number: H03F1/301 ,  H03F3/211 ,  H03F3/45201 ,  H03F3/45237 ,  H03F3/45273 ,  H03F3/4565 ,  H03F2200/555 ,  H03F2203/45336 ,  H03F2203/45372 ,  H03F2203/45508 ,  H03F2203/45594 ,  H03G1/0029 ,  H03G1/0088 ,  H03G3/30

Abstract: An amplifier with adjustable gain including a plurality of differential amplifiers and an output stage circuit is provided. Each of the differential amplifiers has at least one differential pair, two current terminals of each of the differential pairs are coupled by a connection structure, and the connection structure provides a negative feedback resistance. The differential amplifiers commonly receive a differential input signal pair, and output terminals of the differential amplifiers are coupled together. The output stage circuit inverts a voltage on the output terminals of the differential amplifiers to generate an output voltage. A direct current gain of the amplifier with adjustable gain is determined by adjusting at least one of working numbers of the differential amplifiers and the differential pairs.

公开(公告)号：US09946294B2

公开(公告)日：2018-04-17

申请号：US15046425

申请日：2016-02-17

Applicant: Faraday Technology Corp.

Inventor： Chih-Hung Wu

IPC: G11C8/00 ,  G06F1/06 ,  G06F3/06

CPC classification number: G06F1/06 ,  G06F3/0611 ,  G06F3/0653 ,  G06F3/0673

Abstract: A Double Data Rate (DDR) gating method is applied to a memory controller of an associated DDR gating apparatus. The DDR gating method includes: outputting from the memory controller an outward clock signal to a memory, and receiving from the memory a backward clock signal corresponding to the outward clock signal, wherein the backward clock signal is utilized as reference for a data read operation of the memory controller with respect to the memory; and providing an input stage of the memory controller with a reference signal to generate, through single ended receiving of the input stage, gating-related information for performing gating when sampling the backward clock signal, and lengthening time of a preamble of the backward clock signal with aid of the single ended receiving of the input stage, for increasing a detection margin of the preamble.

公开(公告)号：US09773534B2

公开(公告)日：2017-09-26

申请号：US15158589

申请日：2016-05-19

Applicant: Faraday Technology Corp.

Inventor： Kun-Chih Chen ,  Hsiao-An Chuang

IPC: G11C7/10 ,  G11C7/22 ,  G11C8/06

CPC classification number: G11C8/06 ,  G11C7/1039 ,  G11C7/106 ,  G11C15/00 ,  G11C16/26 ,  G11C16/32 ,  G11C2207/2281

Abstract: A non-volatile memory accelerator and a method for speeding up data access are provided. The non-volatile memory accelerator includes a data pre-fetching unit, a cache unit, and an access interface circuit. The data pre-fetching unit has a plurality of line buffers. One of the line buffers provides read data according to a read command, or the data pre-fetching unit reads at least one cache data as the read data according to the read command. The data pre-fetching unit further stores in at least one of the line buffers a plurality of pre-stored data with continuous addresses according to the read command. The cache unit stores the at least one cache data and the pre-stored data with the continuous addresses. The access interface circuit is configured to be an interface circuit of the non-volatile memory.

公开(公告)号：US20170207903A1

公开(公告)日：2017-07-20

申请号：US15173702

申请日：2016-06-05

Applicant: Faraday Technology Corp.

Inventor： Chih-Cheng Chiu

IPC: H04L7/00 ,  H04B3/04

CPC classification number: H04L7/0016 ,  H04B3/04 ,  H04L7/005 ,  H04L25/14

Abstract: A method and apparatus for performing de-skew control are provided, where the method is applied to an electronic device. The method includes: buffering a plurality of data sequences for performing symbol detection on a plurality of channels; according to a first symbol on a first channel, determining corresponding first expected symbols on other channels to determine a plurality of candidate expected symbol positions on the other channels, respectively; according to at least one other symbol on the first channel, within the candidate expected symbol positions on the other channels, eliminating any candidate expected symbol position that does not comply with a predetermined format to obtain a plurality of expected symbol positions on the other channels; and utilizing the expected symbol positions as correct positions of the corresponding first expected symbols on the other channels to control respective data of the data sequences to be synchronously transmitted.

公开(公告)号：US09673808B1

公开(公告)日：2017-06-06

申请号：US15065879

申请日：2016-03-10

Applicant: Faraday Technology Corp.

Inventor： Kai-Neng Tang ,  Chi-Sheng Liao

IPC: H03K5/22 ,  H03K17/22

CPC classification number: H03K17/223

Abstract: A power-on-reset circuit including a first diode-connected transistor, a second diode-connected transistor, a resistor and a current comparator circuit is provided. A cathode of the first diode-connected transistor is coupled to a reference voltage. A first end of the resistor is coupled to a power voltage. A second end of the resistor is coupled to an anode of the first diode-connected transistor. A cathode of the second diode-connected transistor is coupled to the reference voltage. An anode of the second diode-connected transistor is coupled to the first end of the resistor. The current comparator circuit is coupled to the first diode-connected transistor and the second diode-connected transistor. The current comparator circuit compares a current of the first diode-connected transistor with a current of the second diode-connected transistor to obtain a comparing result, wherein the comparing result determines a reset signal.