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    System and method for detecting sleepiness
    82.
    发明授权
    System and method for detecting sleepiness 有权
    用于检测嗜睡的系统和方法

    公开(公告)号：US07887489B2

    公开(公告)日：2011-02-15

    申请号：US12520246

    申请日：2008-08-29

    Applicant: Jae Jin Lee ,  Chung Hwan Kim ,  Min Gun Kim

    Inventor： Jae Jin Lee ,  Chung Hwan Kim ,  Min Gun Kim

    IPC: A61B5/02

    CPC classification number: G08B21/06 ,  A61B5/0205 ,  A61B5/0402 ,  A61B5/0507 ,  A61B5/1102 ,  A61B5/7455 ,  A61B2503/22

    Abstract: The present invention relates to a drowsiness detection method. A heartbeat signal and a breathing signal are detected by exploiting together a scheme and an optical system scheme. The detected signals are applied to respective amplification units, noise signals are eliminated from the detected signals, and noise-free signals are amplified. The amplified signals are applied to a central processing unit, signal processing is processed on the signals, and processed signals are combined. The combined signal is counted, and a warning sound, voice message or vibration is output in a case where a value, obtained by subtracting a counted output value monitored one minute before a current time, from a counted output value monitored two minutes before the current time, falls within a detection range and where, with a passage of time, the value falling within the detection range is successively detected from two to ten times.

    Abstract translation: 本发明涉及一种嗜睡检测方法。 通过一起利用方案和光学系统方案来检测心跳信号和呼吸信号。 检测到的信号被施加到各个放大单元，从检测到的信号中消除噪声信号，并且无噪声信号被放大。 将放大的信号施加到中央处理单元，对信号进行信号处理，并且处理的信号被组合。 对组合的信号进行计数，并且在通过从当前时间之前1分钟监视的计数输出值减去得到的值从在当前的两分钟前监视的计数输出值得到的值的情况下输出警告声音，语音消息或振动 时间落在检测范围内，并且随着时间的流逝，落在检测范围内的值被连续地检测到两到十次。

    Analog-digital converter and on-die thermal sensor including the same
    83.
    发明授权
    Analog-digital converter and on-die thermal sensor including the same 有权
    模拟数字转换器和片上热传感器包括相同的

    公开(公告)号：US07880661B2

    公开(公告)日：2011-02-01

    申请号：US11819816

    申请日：2007-06-29

    Applicant: Chun-Seok Jeong ,  Jae-Jin Lee ,  Joong-Sik Kih ,  Jong-Man Im ,  Jae-Woong Choi ,  Myoung-Jun Chai ,  Kae-Dal Kwack

    Inventor： Chun-Seok Jeong ,  Jae-Jin Lee ,  Joong-Sik Kih ,  Jong-Man Im ,  Jae-Woong Choi ,  Myoung-Jun Chai ,  Kae-Dal Kwack

    IPC: H03M1/50

    CPC classification number: H03M1/56 ,  G01K7/01 ,  G01K2219/00

    Abstract: An on-die thermal sensor includes an integrating analog-digital converter not requiring a negative reference voltage input. The on die thermal sensor includes a band gap unit, an integrating unit and a counting unit. The band gap unit senses a temperature to output a first voltage corresponding to the sensed temperature. The integrating unit integrates a difference between a reference voltage and a comparing voltage to output a second voltage wherein the comparing voltage has a voltage level higher than that of the reference voltage. The counting unit counts clocks of a clock signal input thereto until the second voltage reaches the first voltage, thereby outputting a thermal code corresponding to the voltage level of the first voltage.

    Abstract translation: 片上热传感器包括不需要负参考电压输入的积分模数转换器。 管芯热传感器包括带隙单元，积分单元和计数单元。 带隙单元感测温度以输出对应于感测温度的第一电压。 积分单元将参考电压和比较电压之间的差分相加以输出第二电压，其中比较电压的电压电平高于参考电压的电压电平。 计数单元对输入的时钟信号的时钟进行计数，直到第二电压达到第一电压，从而输出与第一电压的电压电平对应的热代码。

    Impedance matching circuit and semiconductor memory device with the same
    84.
    发明授权
    Impedance matching circuit and semiconductor memory device with the same 有权
    阻抗匹配电路和半导体存储器件相同

    公开(公告)号：US07710143B2

    公开(公告)日：2010-05-04

    申请号：US11967659

    申请日：2007-12-31

    Applicant: Chun-Seok Jeong ,  Jae-Jin Lee

    Inventor： Chun-Seok Jeong ,  Jae-Jin Lee

    IPC: H03K17/16 ,  H03K19/003

    CPC classification number: H03K19/0005 ,  G11C5/063 ,  G11C7/1048 ,  G11C2207/2254

    Abstract: An impedance matching circuit of a semiconductor memory device performs a ZQ calibration with initial values that reflect an offset error according to variations in a manufacturing process. The impedance matching circuit includes a first pull-down resistance unit, a first pull-up resistance unit, and a code generation unit. The first pull-down resistance unit supplies a ground voltage to a first node, thereby determining an initial pull-down code. The first pull-up resistance unit supplies a supply voltage to the first node, thereby determining an initial pull-up code or a voltage level on the first node. The code generation unit generates pull-down and pull-up calibration codes using the initial pull-down and pull-up codes as respective initial values.

    Abstract translation: 半导体存储器件的阻抗匹配电路根据制造过程中的变化，以反映偏移误差的初始值来执行ZQ校准。 阻抗匹配电路包括第一下拉电阻单元，第一上拉电阻单元和代码生成单元。 第一下拉电阻单元向第一节点提供接地电压，从而确定初始下拉代码。 第一上拉电阻单元向第一节点提供电源电压，从而确定第一节点上的初始上拉代码或电压电平。 代码生成单元使用初始下拉和上拉代码作为相应的初始值生成下拉和上拉校准代码。

    Delay locked loop circuit
    87.
    发明授权
    Delay locked loop circuit 有权
    延时锁定回路电路

    公开(公告)号：US07605622B2

    公开(公告)日：2009-10-20

    申请号：US11478094

    申请日：2006-06-30

    Applicant: Hoon Choi ,  Jae-Jin Lee

    Inventor： Hoon Choi ,  Jae-Jin Lee

    IPC: H03L7/06

    CPC classification number: H03L7/0814 ,  G06F7/68 ,  H03L7/0805

    Abstract: A DLL of a memory device having a normal mode and a power down mode includes a clock buffer for buffering an external clock signal to output an internal clock signal. A power down mode controller generates a power down mode control signal to define the normal mode or the power down mode in response to a clock enable signal. A source clock generation unit receives the internal clock signal to generate a DLL source clock signal under the control of the power down mode control signal. A phase update unit performs a phase update operation based on the DLL source clock signal to output a DLL clock signal.

    Abstract translation: 具有正常模式和掉电模式的存储器件的DLL包括用于缓冲外部时钟信号以输出内部时钟信号的时钟缓冲器。 断电模式控制器响应于时钟使能信号产生掉电模式控制信号以定义正常模式或掉电模式。 源时钟生成单元在停电模式控制信号的控制下接收内部时钟信号以产生DLL源时钟信号。 相位更新单元基于DLL源时钟信号执行相位更新操作，以输出DLL时钟信号。

    Semiconductor memory device
    88.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07579904B2

    公开(公告)日：2009-08-25

    申请号：US11623569

    申请日：2007-01-16

    Applicant: Jae-Hyuk Im ,  Jae-Jin Lee

    Inventor： Jae-Hyuk Im ,  Jae-Jin Lee

    IPC: G05F1/10

    CPC classification number: G11C5/14 ,  G11C11/406 ,  G11C11/4074 ,  G11C2211/4068

    Abstract: Disclosed herein is an internal voltage generation circuit of a semiconductor memory device which is capable of supplying voltages of different levels to a column path & control logic and data path & control logic in the memory device according to different operation modes of the memory device. The column path & control logic and data path & control logic are applied with a normal operating voltage when they are involved in the current operation mode of the memory device, whereas with a lower voltage when they are not involved. Therefore, the present invention has the effect of efficiently managing internal voltages of the semiconductor memory device and reducing current leakage of the memory device and, in turn, unnecessary power consumption thereof.

    Abstract translation: 本文公开了一种半导体存储器件的内部电压产生电路，其能够根据存储器件的不同操作模式向存储器件中的列路径和控制逻辑以及数据路径和控制逻辑提供不同电平的电压。 列路径和控制逻辑以及数据路径和控制逻辑在其参与存储器件的当前操作模式时被应用于正常工作电压，而当它们不涉及时具有较低的电压。 因此，本发明具有有效地管理半导体存储器件的内部电压并且减少存储器件的电流泄漏的效果，并且反过来又导致其不必要的功耗。

    SEMICONDUCTOR DEVICE HAVING INPUT CIRCUIT MINIMIZING INFLUENCE OF VARIATIONS IN INPUT SIGNALS
    89.
    发明申请
    SEMICONDUCTOR DEVICE HAVING INPUT CIRCUIT MINIMIZING INFLUENCE OF VARIATIONS IN INPUT SIGNALS 失效
    具有输入电路的半导体器件最小化输入信号变化的影响

    公开(公告)号：US20090184757A1

    公开(公告)日：2009-07-23

    申请号：US12138554

    申请日：2008-06-13

    Applicant: Mi Hye KIM ,  Jae Jin LEE

    Inventor： Mi Hye KIM ,  Jae Jin LEE

    IPC: G05F1/10

    CPC classification number: G11C7/1078 ,  G11C7/1084

    Abstract: A semiconductor device stabilizes an operation of an input buffer. A semiconductor device includes an input potential detection unit, an input buffer, and a current sink unit. The input potential detection unit outputs a detection signal in response to a level of an input signal. The input buffer buffers the input signal by differentially amplifying the input signal through a first current sink unit. The current sink unit receives the detection signal, and in response to the detection signal, performs an auxiliary differential amplifying operation with respect to the input signal buffered by the input buffer.

    Abstract translation: 半导体器件稳定输入缓冲器的操作。 半导体器件包括输入电位检测单元，输入缓冲器和电流吸收单元。 输入电位检测单元响应于输入信号的电平输出检测信号。 输入缓冲器通过第一电流吸收单元对输入信号进行差分放大来缓冲输入信号。 当前的接收单元接收检测信号，并且响应于检测信号，对由输入缓冲器缓冲的输入信号执行辅助差分放大操作。

    SEMICONDUCTOR DEVICE HAVING INPUT CIRCUIT WITH AUXILIARY CURRENT SINK
    90.
    发明申请
    SEMICONDUCTOR DEVICE HAVING INPUT CIRCUIT WITH AUXILIARY CURRENT SINK 失效
    具有辅助电流波形的输入电路的半导体器件

    公开(公告)号：US20090184737A1

    公开(公告)日：2009-07-23

    申请号：US12138024

    申请日：2008-06-12

    Applicant: Mi Hye Kim ,  Jae Jin Lee

    Inventor： Mi Hye Kim ,  Jae Jin Lee

    IPC: H03B1/00

    CPC classification number: H03K19/00323 ,  G11C7/1078 ,  G11C7/1084 ,  H03K19/01721 ,  H03K19/01742 ,  H03K19/018528 ,  H03K19/09429

    Abstract: A semiconductor device stabilizes an operation of an input buffer. A semiconductor device includes an input potential detection unit outputting a detection signal in response to a level of an input signal. An input buffer buffers the input signal by performing a differential amplifying operation through a first current sink unit. A second current sink unit, sharing an output with the input buffer, differentially amplifies the input signal of the input buffer in response to a level of the detection signal.

    Abstract translation: 半导体器件稳定输入缓冲器的操作。 半导体器件包括输入电位检测单元，其响应于输入信号的电平输出检测信号。 输入缓冲器通过执行通过第一电流吸收器单元的差分放大操作来缓冲输入信号。 与输入缓冲器共享输出的第二电流宿单元响应于检测信号的电平差分地放大输入缓冲器的输入信号。

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