公开(公告)号：US08796561B1

公开(公告)日：2014-08-05

申请号：US12573466

申请日：2009-10-05

申请人： Christopher M. Scanlan ,  Roger D. St. Amand ,  Jae Dong Kim

发明人： Christopher M. Scanlan ,  Roger D. St. Amand ,  Jae Dong Kim

IPC分类号： H01L23/48 ,  H05K1/16 ,  H05K1/18 ,  H01L23/04

CPC分类号： H01L24/19 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/16 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16265 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32265 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92125 ,  H01L2924/14 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/4007 ,  H05K3/465 ,  H05K2203/1469 ,  H01L2924/00012 ,  H01L2924/00

摘要： A fan out build up substrate stackable package includes an electronic component having an active surface including a bond pad. A package body encloses the electronic component, the package body having a first surface coplanar with the active surface of the electronic component. A buildup dielectric layer is applied to the active surface of the electronic component and the first surface of the package body. A circuit pattern is formed within the first buildup dielectric layer and electrically connected to the bond pad, the first circuit pattern including via capture pads. Via capture pad apertures extend through the package body and expose the via capture pads. In this manner, direct connection to the first circuit pattern, i.e., the first metal layer, of the fan out build up substrate stackable package is facilitated. Further, the fan out build up substrate stackable package is extremely thin resulting in extremely thin stacked assemblies.

摘要翻译： 扇出的基板可堆叠封装包括具有包括接合焊盘的有源表面的电子部件。 封装体包围电子部件，封装主体具有与电子部件的有效表面共面的第一表面。 将积聚电介质层施加到电子部件的有源表面和封装主体的第一表面。 电路图案形成在第一累积电介质层内并电连接到接合焊盘，第一电路图案包括通孔捕获垫。 通过捕获垫孔径延伸穿过封装主体并暴露通孔捕获垫。 以这种方式，便利地直接连接到扇形器的第一电路图案，即第一金属层，从而构建基板可堆叠封装。 此外，扇出构建基板可堆叠封装非常薄，导致非常薄的堆叠组件。

公开(公告)号：US08207022B1

公开(公告)日：2012-06-26

申请号：US12931326

申请日：2011-01-27

申请人： Robert Francis Darveaux ,  Michael Barrow ,  Miguel Angel Jimarez ,  Jae Dong Kim ,  Dae Keun Park ,  Ki Wook Lee ,  Ju Hoon Yoon

发明人： Robert Francis Darveaux ,  Michael Barrow ,  Miguel Angel Jimarez ,  Jae Dong Kim ,  Dae Keun Park ,  Ki Wook Lee ,  Ju Hoon Yoon

IPC分类号： B29C31/00 ,  H01L23/29

CPC分类号： H01L23/28 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/562 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105

摘要： An exposed die overmolded flip chip package includes a substrate. A die is flip chip mounted to an upper surface of the substrate. The package further includes a mold cap filling a space between an active surface of the die and the upper surface of the substrate. The mold cap includes a principal surface, sidewalls extending from the upper surface of the substrate to the principal surface, an annular surface coplanar with the inactive surface of the die and extending outward from a peripheral edge of the inactive surface of the die, and protruding surfaces extending between the principal surface and the annular surface. The mold cap does not cover the inactive surface of the die such that heat transfer from the die to the ambient environment is maximized and the package thickness is minimized.

摘要翻译： 曝光的芯片包覆成型的倒装芯片封装包括衬底。 芯片安装在基板的上表面上。 该包装还包括填充模具的活性表面和基材的上表面之间的空间的模具盖。 模具帽包括主表面，从基板的上表面延伸到主表面的侧壁，与模具的非活性表面共面并从模具的非活性表面的外围边缘向外延伸的环形表面，并且突出 表面在主表面和环形表面之间延伸。 模具盖不覆盖模具的非活性表面，使得从模具到周围环境的热传递最大化并且封装厚度最小化。

公开(公告)号：US07982298B1

公开(公告)日：2011-07-19

申请号：US12327763

申请日：2008-12-03

申请人： Dae Byoung Kang ,  Sung Jin Yang ,  Jung Tae Ok ,  Jae Dong Kim

发明人： Dae Byoung Kang ,  Sung Jin Yang ,  Jung Tae Ok ,  Jae Dong Kim

IPC分类号： H01L23/48

CPC分类号： H01L25/03 ,  H01L23/3121 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/0002 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552

摘要： In accordance with the present invention, there is provided multiple embodiments of a package-in-package semiconductor device including shortened electrical signal paths to optimize electrical performance. In each embodiment, the semiconductor device comprises a substrate having a conductive pattern formed thereon. In certain embodiments, a semiconductor package and one or more semiconductor dies are vertically stacked upon the substrate, and placed into electrical communication with the conductive pattern thereof. One or more of the semiconductor dies may include through-silicon vias formed therein for facilitating the electrical connection thereof to the conductive pattern of the substrate or to other electronic components within the vertical stack. Similarly, the semiconductor package may be provided with through-mold vias to facilitate the electrical connection thereof to other electronic components within the vertical stack. In other embodiments of the present invention, a semiconductor die which is electrically connected to the conductive pattern of the substrate is encapsulated with an inner package body which itself is formed to include through-mold vias used to facilitate the electrical connection thereof to another semiconductor die stacked thereon. In each embodiment of the semiconductor device, the vertically stacked electronic components thereof may be covered with a package body which also partially covers the substrate.

摘要翻译： 根据本发明，提供了包装封装半导体器件的多个实施例，其包括缩短的电信号路径以优化电性能。 在每个实施例中，半导体器件包括其上形成有导电图案的衬底。 在某些实施例中，半导体封装和一个或多个半导体管芯垂直堆叠在衬底上，并与其导电图案电连通。 一个或多个半导体管芯可以包括形成在其中的穿硅通孔，以便于其与衬底的导电图案或垂直堆叠内的其他电子部件的电连接。 类似地，半导体封装可以设置有通孔通孔，以便于其与垂直堆叠内的其它电子部件的电连接。 在本发明的其他实施例中，电连接到衬底的导电图案的半导体管芯被封装成内部封装本体，内部封装本体形成为包括用于促进其与另一半导体管芯的电连接的通孔通孔 堆叠在其上。 在半导体器件的每个实施例中，其垂直堆叠的电子部件可以被也部分地覆盖衬底的封装体覆盖。

公开(公告)号：US20080008171A1

公开(公告)日：2008-01-10

申请号：US11770417

申请日：2007-06-28

申请人： YOUNG-SOO CHOI ,  BYEONG-SOOK BAE ,  JAE-DONG KIM ,  EUN-HO KIM

发明人： YOUNG-SOO CHOI ,  BYEONG-SOOK BAE ,  JAE-DONG KIM ,  EUN-HO KIM

IPC分类号： H04L12/56

CPC分类号： H04L29/12367 ,  H04L29/12264 ,  H04L61/2046 ,  H04L61/2514 ,  H04L63/1416 ,  H04L69/22

摘要： Disclosed is an IP sharer detecting and intercepting system and method. According to the IP sharer detecting and intercepting method, all the IP packets transmitted through the network are detected, an ID value of the IP header is extracted from the detected IP packets, and an IP sharer user is estimated based on the number of states of ID values for the same IP. A notice packet is transmitted to the estimated IP sharer user to detect a private IP of the IP sharer user, it is determined whether the IP sharer user uses the IP sharer based on the detected private IP, and the checked IP sharer user's Internet connection is intercepted. In this instance, a notice packet for introducing an entrance to a normal cable is generated to the IP sharer user before the checked IP sharer user's Internet connection is intercepted.

摘要翻译： 公开了IP分享者检测和拦截系统及方法。 根据IP分享者检测和拦截方法，检测到通过网络传输的所有IP分组，从检测到的IP分组中提取IP报头的ID值，并根据状态数量估计IP分享者用户数 相同IP的ID值。 通知数据包被传送到估计的IP共享者用户以检测IP共享者用户的专用IP，确定IP共享者用户是否基于检测到的私有IP使用IP共享者，并且所检查的IP共享者用户的因特网连接是 截获 在这种情况下，在被检查的IP共享者用户的因特网连接被拦截之前，向IP共享者用户生成用于引入普通电缆入口的通知包。

公开(公告)号：US06642610B2

公开(公告)日：2003-11-04

申请号：US09745265

申请日：2000-12-20

申请人： Young Kuk Park ,  Byung Joon Han ,  Jae Dong Kim

发明人： Young Kuk Park ,  Byung Joon Han ,  Jae Dong Kim

IPC分类号： H01L2302

CPC分类号： H01L24/85 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/48479 ,  H01L2224/4848 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/85051 ,  H01L2224/85181 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/4554

摘要： A semiconductor package including plural semiconductor chips, and a wire bonding step for electrically interconnecting the semiconductor chips, are disclosed. In an exemplary method, a substrate is provided. Conductive circuit patterns are provided outside of a chip mounting region of the substrate, and conductive transfer patterns are provided proximate to the chip mounting region. Chips are placed in the chip mounting region. Conductive wires are bonded between input/output pads of a first chip and respective transfer patterns, and other conductive wires are bonded between input/output pads of a second chip and the same transfer patterns, thereby electrically connecting respective input/output pads of the two chips through a pair of bond wires and an intermediate transfer pattern.

公开(公告)号：US09839898B2

公开(公告)日：2017-12-12

申请号：US15010423

申请日：2016-01-29

申请人： Dal Ryung Park ,  Bong Gyu Kim ,  Jae Dong Kim ,  Jin Wook Kim ,  Keun Yong Cho ,  Chul Hee Jeon ,  Min Ho Bae ,  Chan Sik Park

发明人： Dal Ryung Park ,  Bong Gyu Kim ,  Jae Dong Kim ,  Jin Wook Kim ,  Keun Yong Cho ,  Chul Hee Jeon ,  Min Ho Bae ,  Chan Sik Park

IPC分类号： C01B3/38 ,  C01B3/48 ,  B01J19/00 ,  B01J19/24 ,  B01J8/04

CPC分类号： B01J19/245 ,  B01J8/0469 ,  B01J8/0473 ,  B01J8/0496 ,  B01J2208/00185 ,  B01J2208/00194 ,  B01J2208/00203 ,  B01J2208/00504 ,  B01J2219/00078 ,  B01J2219/00081 ,  B01J2219/00083 ,  B01J2219/0009 ,  B01J2219/00092 ,  B01J2219/00094 ,  B01J2219/00157 ,  B01J2219/24 ,  C01B3/38 ,  C01B3/48 ,  C01B2203/0233 ,  C01B2203/0288 ,  C01B2203/0495 ,  C01B2203/0816 ,  Y02P20/124

摘要： Disclosed is a fuel processor. The fuel processor includes: a steam reformer unit configured to be disposed at an upper portion in a casing; a heat exchanger unit configured to be disposed at a lower portion of the steam reformer unit; a high temperature shift reforming unit configured to be disposed at a lower portion of the heat exchanger unit; a low temperature shift reforming unit configured to be disposed while enclosing an outer portion of the high temperature shift reforming unit; and a heat exchange chamber configured to be disposed at a lower portion of the high temperature shift reforming unit and exchange heat between reformed gas and a heat exchange fluid supplied through a channel part formed to drain the reformed gas and combustion gas and supply the heat exchange fluid.

公开(公告)号：US20160236166A1

公开(公告)日：2016-08-18

申请号：US15010423

申请日：2016-01-29

申请人： DAL RYUNG PARK ,  BONG GYU KIM ,  JAE DONG KIM ,  JIN WOOK KIM ,  KEUN YONG CHO ,  CHUL HEE JEON ,  MIN HO BAE ,  CHAN SIK PARK

发明人： DAL RYUNG PARK ,  BONG GYU KIM ,  JAE DONG KIM ,  JIN WOOK KIM ,  KEUN YONG CHO ,  CHUL HEE JEON ,  MIN HO BAE ,  CHAN SIK PARK

IPC分类号： B01J19/24 ,  C01B3/38

CPC分类号： B01J19/245 ,  B01J8/0469 ,  B01J8/0473 ,  B01J8/0496 ,  B01J2208/00185 ,  B01J2208/00194 ,  B01J2208/00203 ,  B01J2208/00504 ,  B01J2219/00078 ,  B01J2219/00081 ,  B01J2219/00083 ,  B01J2219/0009 ,  B01J2219/00092 ,  B01J2219/00094 ,  B01J2219/00157 ,  B01J2219/24 ,  C01B3/38 ,  C01B3/48 ,  C01B2203/0233 ,  C01B2203/0288 ,  C01B2203/0495 ,  C01B2203/0816 ,  Y02P20/124

摘要： Disclosed is a fuel processor. The fuel processor includes: a steam reformer unit configured to be disposed at an upper portion in a casing; a heat exchanger unit configured to be disposed at a lower portion of the steam reformer unit; a high temperature shift reforming unit configured to be disposed at a lower portion of the heat exchanger unit; a low temperature shift reforming unit configured to be disposed while enclosing an outer portion of the high temperature shift reforming unit; and a heat exchange chamber configured to be disposed at a lower portion of the high temperature shift reforming unit and exchange heat between reformed gas and a heat exchange fluid supplied through a channel part formed to drain the reformed gas and combustion gas and supply the heat exchange fluid.

摘要翻译： 公开了一种燃料处理器。 燃料处理器包括：蒸汽重整器单元，被配置为设置在壳体的上部; 构造成设置在所述蒸汽重整器单元的下部的热交换器单元; 构造成设置在所述热交换器单元的下部的高温变换重整单元; 低温变换重整单元，其构造成在包围高温变换重整单元的外部部分的同时设置; 以及热交换室，其被配置为设置在所述高温变换重整单元的下部，并且在重整气体和通过形成为排出重整气体和燃烧气体的通道部分供应的热交换流体之间进行热交换，并提供热交换 流体。

公开(公告)号：US08089148B1

公开(公告)日：2012-01-03

申请号：US12539116

申请日：2009-08-11

申请人： Jun Su Lee ,  Min Jae Lee ,  Jae Dong Kim ,  Jae Jin Lee ,  Min Yoo ,  Byung Jun Kim

发明人： Jun Su Lee ,  Min Jae Lee ,  Jae Dong Kim ,  Jae Jin Lee ,  Min Yoo ,  Byung Jun Kim

IPC分类号： H01L23/48

CPC分类号： H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/1579 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01083 ,  H01L2224/32225 ,  H01L2924/00012

摘要： A circuit board has an insulative layer including a first surface and a second surface opposite to the first surface. A plurality of electrically conductive patterns is formed on the first surface of the insulative layer. Conductive lands are formed in a die mounting region of the first surface of the insulative layer and electrically connected to one of the plurality of conductive patterns on the first surface. An extending pattern extends from the conductive lands to outside of the mounting region. A protective layer covers the first surface of the insulative layer and the electrically conductive patterns. A trench is formed in the protective layer to expose the conductive lands and the extending patterns.

摘要翻译： 电路板具有包括与第一表面相对的第一表面和第二表面的绝缘层。 在绝缘层的第一表面上形成多个导电图案。 导电焊盘形成在绝缘层的第一表面的管芯安装区域中，并且与第一表面上的多个导电图案之一电连接。 延伸图案从导电焊盘延伸到安装区域的外部。 保护层覆盖绝缘层的第一表面和导电图案。 在保护层中形成沟槽以暴露导电焊盘和延伸图案。

公开(公告)号：US07898093B1

公开(公告)日：2011-03-01

申请号：US11592889

申请日：2006-11-02

申请人： Robert Francis Darveaux ,  Michael Barrow ,  Miguel Angel Jimarez ,  Jae Dong Kim ,  Dae Keun Park ,  Ki Wook Lee ,  Ju Hoon Yoon

发明人： Robert Francis Darveaux ,  Michael Barrow ,  Miguel Angel Jimarez ,  Jae Dong Kim ,  Dae Keun Park ,  Ki Wook Lee ,  Ju Hoon Yoon

IPC分类号： H01L23/28

CPC分类号： H01L23/28 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/562 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105

摘要： An exposed die overmolded flip chip package includes a substrate. A die is flip chip mounted to an upper surface of the substrate. The package further includes a mold cap filling a space between an active surface of the die and the upper surface of the substrate. The mold cap includes a principal surface, sidewalls extending from the upper surface of the substrate to the principal surface, an annular surface coplanar with the inactive surface of the die and extending outward from a peripheral edge of the inactive surface of the die, and protruding surfaces extending between the principal surface and the annular surface. The mold cap does not cover the inactive surface of the die such that heat transfer from the die to the ambient environment is maximized and the package thickness is minimized.

摘要翻译： 曝光的芯片包覆成型的倒装芯片封装包括衬底。 芯片安装在基板的上表面上。 该包装还包括填充模具的活性表面和基材的上表面之间的空间的模具盖。 模具帽包括主表面，从基板的上表面延伸到主表面的侧壁，与模具的非活性表面共面并从模具的非活性表面的外围边缘向外延伸的环形表面，并且突出 表面在主表面和环形表面之间延伸。 模具盖不覆盖模具的非活性表面，使得从模具到周围环境的热传递最大化并且封装厚度最小化。

公开(公告)号：US20090184852A1

公开(公告)日：2009-07-23

申请号：US12232205

申请日：2008-09-12

申请人： Keon Joon Ahn ,  Jae Hun Bae ,  Jae Dong Kim ,  Hwan Soo Bae ,  Kyong Ho Park

发明人： Keon Joon Ahn ,  Jae Hun Bae ,  Jae Dong Kim ,  Hwan Soo Bae ,  Kyong Ho Park

IPC分类号： H03K17/94

CPC分类号： G06F1/169 ,  G05G2009/04759 ,  G06F1/1626 ,  G06F3/03547 ,  G06F3/042 ,  G06F2203/0338

摘要： An optical joystick and portable electronic device having the same are disclosed, by which malfunctions of the optical joystick due to sunlight or external illumination light are prevented or minimized. Therefore, precision of the optical joystick can be enhanced. The optical joystick according to the present invention includes an infrared light source, a cover part having a contacting surface for a contact by a subject, a light-receiving part detecting the infrared ray, and an optical member provided on an light path of the infrared ray traveling from the cover part toward the light-receiving part, wherein the cover part comprises a cover base and an infrared ray pass layer blocking out external noisy light on a predetermined band and passing substantially a wavelength band of infrared rays.

摘要翻译： 公开了具有该光学操纵杆和便携式电子设备的光学操纵杆和便携式电子设备，由此防止或最小化由于太阳光或外部照明光引起的光学操纵杆的故障。 因此，可以提高光学操纵杆的精度。 根据本发明的光学操纵杆包括红外光源，具有用于与被摄体接触的接触表面的盖部分，检测红外线的光接收部分和设置在红外线的光路上的光学部件 其中所述盖部分包括盖基和红外线通过层，其阻挡预定带上的外部噪声光并且基本上通过红外线的波长带。