公开(公告)号：US07615441B2

公开(公告)日：2009-11-10

申请号：US11998236

申请日：2007-11-29

Applicant: Justin K. Brask ,  Jack Kavalieros ,  Mark L. Doczy ,  Matthew V. Metz ,  Suman Datta ,  Uday Shah ,  Gilbert Dewey ,  Robert S. Chau

Inventor： Justin K. Brask ,  Jack Kavalieros ,  Mark L. Doczy ,  Matthew V. Metz ,  Suman Datta ,  Uday Shah ,  Gilbert Dewey ,  Robert S. Chau

IPC: H01L21/8242

CPC classification number: H01L21/0228 ,  H01L21/02052 ,  H01L21/02175 ,  H01L21/28167 ,  H01L21/3141 ,  H01L29/513 ,  H01L29/517 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A buffer layer and a high-k metal oxide dielectric may be formed over a smooth silicon substrate. The substrate smoothness may reduce column growth of the high-k metal oxide gate dielectric. The surface of the substrate may be saturated with hydroxyl terminations prior to deposition.

Abstract translation: 可以在平滑的硅衬底上形成缓冲层和高k金属氧化物电介质。 衬底平滑度可能降低高k金属氧化物栅极电介质的柱生长。 在沉积之前，衬底的表面可能被羟基终止物饱和。

公开(公告)号：US07531393B2

公开(公告)日：2009-05-12

申请号：US11373776

申请日：2006-03-09

Applicant: Brian S. Doyle ,  Suman Datta ,  Been-Yih Jin ,  Robert Chau

Inventor： Brian S. Doyle ,  Suman Datta ,  Been-Yih Jin ,  Robert Chau

IPC: H01L21/84

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/78687

Abstract: An embodiment is a non-planar MOS transistor structure including a strained channel region. The combination of a non-planar MOS transistor structure, and in particular an NMOS tri-gate transistor, with the benefits of a strained channel yields improved transistor drive current, switching speed, and decreased leakage current for a given gate length width versus a non-planar MOS structure with an unstrained channel or planar MOS structure including a strained channel.

Abstract translation: 一个实施例是包括应变通道区域的非平面MOS晶体管结构。 具有应变通道优点的非平面MOS晶体管结构，特别是NMOS三栅极晶体管的组合产生了对于给定栅极长度宽度相对于非晶体管的晶体管驱动电流，开关速度和降低的漏电流 具有包含应变通道的无约束通道或平面MOS结构的平面MOS结构。

公开(公告)号：US07524727B2

公开(公告)日：2009-04-28

申请号：US11322745

申请日：2005-12-30

Applicant: Gilbert Dewey ,  Mark L. Doczy ,  Suman Datta ,  Justin K. Brask ,  Matthew V. Metz

Inventor： Gilbert Dewey ,  Mark L. Doczy ,  Suman Datta ,  Justin K. Brask ,  Matthew V. Metz

IPC: H01L21/336

CPC classification number: H01L29/513 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66795 ,  H01L29/78

Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.

Abstract translation: 本文公开了半导体器件和新型半导体器件的制造方法。 示例性的方法包括在执行任何高温处理步骤之前，在栅介质层上原位溅射覆盖层。

公开(公告)号：US20090075445A1

公开(公告)日：2009-03-19

申请号：US12313368

申请日：2008-11-19

Applicant: Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew V. Metz ,  Suman Datta ,  Brian S. Doyle ,  Robert S. Chau ,  Everett X. Wang ,  Philippe Matagne ,  Lucian Shifren ,  Been Y. Jin ,  Mark Stettler ,  Martin D. Giles

Inventor： Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew V. Metz ,  Suman Datta ,  Brian S. Doyle ,  Robert S. Chau ,  Everett X. Wang ,  Philippe Matagne ,  Lucian Shifren ,  Been Y. Jin ,  Mark Stettler ,  Martin D. Giles

IPC: H01L21/336

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848 ,  Y10S438/933

Abstract: A transistor may be formed of different layers of silicon germanium, a lowest layer having a graded germanium concentration and upper layers having constant germanium concentrations such that the lowest layer is of the form Si1-xGex. The highest layer may be of the form Si1-yGey on the PMOS side. A source and drain may be formed of epitaxial silicon germanium of the form Si1-zGez on the PMOS side. In some embodiments, x is greater than y and z is greater than x in the PMOS device. Thus, a PMOS device may be formed with both uniaxial compressive stress in the channel direction and in-plane biaxial compressive stress. This combination of stress may result in higher mobility and increased device performance in some cases.

Abstract translation: 晶体管可以由不同的硅锗层形成，具有梯度锗浓度的最低层和具有恒定锗浓度的上层，使得最底层具有Si1-xGex形式。 最高层可以是PMOS侧的Si1-yGey形式。 源极和漏极可以由PMOS侧的Si1-zGez形式的外延硅锗形成。 在一些实施例中，在PMOS器件中，x大于y且z大于x。 因此，PMOS器件可以在沟道方向上具有单轴压应力和面内双轴压应力。 在某些情况下，这种压力的组合可能导致更高的移动性和增加的设备性能。

公开(公告)号：US20090042405A1

公开(公告)日：2009-02-12

申请号：US12157796

申请日：2008-06-12

Applicant: Mark L. Doczy ,  Justin K. Brask ,  Jack Kavalieros ,  Uday Shah ,  Matthew V. Metz ,  Suman Datta ,  Ramune Nagisetty ,  Robert S. Chau

Inventor： Mark L. Doczy ,  Justin K. Brask ,  Jack Kavalieros ,  Uday Shah ,  Matthew V. Metz ,  Suman Datta ,  Ramune Nagisetty ,  Robert S. Chau

IPC: H01L21/469

CPC classification number: H01L21/823842

Abstract: A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, a trench within the first dielectric layer, and a second dielectric layer on the substrate. The second dielectric layer has a first part that is formed in the trench and a second part. After a first metal layer with a first workfunction is formed on the first and second parts of the second dielectric layer, part of the first metal layer is converted into a second metal layer with a second workfunction.

Abstract translation: 描述制造半导体器件的方法。 该方法包括在衬底上形成第一电介质层，在第一介电层内形成沟槽，在衬底上形成第二电介质层。 第二电介质层具有形成在沟槽中的第一部分和第二部分。 在第二电介质层的第一和第二部分上形成具有第一功函数的第一金属层之后，第一金属层的一部分被转换成具有第二功函数的第二金属层。

公开(公告)号：US20090001474A1

公开(公告)日：2009-01-01

申请号：US11823892

申请日：2007-06-29

Applicant: Suman Datta ,  Titash Rakshit ,  Jack T. Kavalieros ,  Brian S. Doyle

Inventor： Suman Datta ,  Titash Rakshit ,  Jack T. Kavalieros ,  Brian S. Doyle

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/785 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

Abstract: In one embodiment of the invention, a non-planar transistor includes a gate electrode and multiple fins. A trench contact is coupled to the fins. The contact bottom is formed above the substrate and does not directly contact the substrate. The contact bottom is higher than the gate top.

Abstract translation: 在本发明的一个实施例中，非平面晶体管包括栅电极和多个散热片。 沟槽接触件连接到鳍片。 接触底部形成在衬底上方，并且不直接接触衬底。 触点底部高于门顶。

公开(公告)号：US07456476B2

公开(公告)日：2008-11-25

申请号：US10607769

申请日：2003-06-27

Applicant: Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Rafael Rios ,  Tom Linton ,  Suman Datta

Inventor： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Rafael Rios ,  Tom Linton ,  Suman Datta

IPC: H01L29/786

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/66795

Abstract: A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top surface of the semiconductor body on the laterally opposite sidewalls of the semiconductor body and on at least a portion of the bottom surface of semiconductor body. A gate electrode is formed on the gate dielectric, on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of semiconductor body and beneath the gate dielectric on the bottom surface of the semiconductor body. A pair source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

Abstract translation: 描述了非平面半导体器件及其制造方法。 非平面半导体器件包括半导体本体，该半导体本体具有与形成在绝缘基板上方的底表面相对的顶表面，其中半导体本体具有一对横向相对的侧壁。 在半导体本体的横向相对的侧壁和半导体本体的底表面的至少一部分上的半导体本体的顶表面上形成栅极电介质。 栅极电极形成在半导体本体的顶表面上并与半导体本体的横向相对的侧壁上的栅电介质相邻并位于半导体本体的底表面上的栅电介质之下的栅电介质上。 在栅电极的相对侧的半导体本体中形成一对源/漏区。

公开(公告)号：US07449373B2

公开(公告)日：2008-11-11

申请号：US11394614

申请日：2006-03-31

Applicant: Brian S. Doyle ,  Suman Datta ,  Jack T. Kavalieros ,  Amlan Majumdar

Inventor： Brian S. Doyle ,  Suman Datta ,  Jack T. Kavalieros ,  Amlan Majumdar

IPC: H01L21/00

CPC classification number: H01L21/26586 ,  H01L29/66803 ,  H01L29/7851

Abstract: A method for ion implanting a tip source and drain region and halo region for a tri-gate field-effect transistor is described. A silicon body is implanted, in one embodiment, from six different angles to obtain ideal regions.

Abstract translation: 描述了用于三栅极场效应晶体管的用于离子注入尖端源极和漏极区域和晕圈区域的方法。 在一个实施例中，从六个不同的角度植入硅体，以获得理想的区域。

公开(公告)号：US07442983B2

公开(公告)日：2008-10-28

申请号：US11390892

申请日：2006-03-27

Applicant: Mark L. Doczy ,  Gilbert Dewey ,  Suman Datta ,  Sangwoo Pae ,  Justin K. Brask ,  Jack Kavalieros ,  Matthew V. Metz ,  Adrian B. Sherrill ,  Markus Kuhn ,  Robert S. Chau

Inventor： Mark L. Doczy ,  Gilbert Dewey ,  Suman Datta ,  Sangwoo Pae ,  Justin K. Brask ,  Jack Kavalieros ,  Matthew V. Metz ,  Adrian B. Sherrill ,  Markus Kuhn ,  Robert S. Chau

IPC: H01L27/108

CPC classification number: H01L21/0214 ,  H01L21/02142 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/3144 ,  H01L21/31691 ,  H01L28/56 ,  H01L29/517 ,  H01L29/518

Abstract: A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.

Abstract translation: 描述制造半导体器件的方法。 该方法包括在衬底上形成氧化物层，并在氧化物层上形成高k电介质层。 然后将氧化物层和高k电介质层在足够的温度下退火足够的时间以产生具有渐变介电常数的栅极电介质。

公开(公告)号：US20080237735A1

公开(公告)日：2008-10-02

申请号：US11731162

申请日：2007-03-30

Applicant: Jack T. Kavalieros ,  Suman Datta ,  Robert S. Chau ,  David L. Kencke

Inventor： Jack T. Kavalieros ,  Suman Datta ,  Robert S. Chau ,  David L. Kencke

IPC: H01L27/06 ,  H01L21/8249

CPC classification number: H01L21/8249 ,  H01L21/28273 ,  H01L27/0705 ,  H01L29/0821 ,  H01L29/66825 ,  H01L29/73 ,  H01L29/7606 ,  H01L29/7881

Abstract: A hetero-BiMOS injection system comprises a MOSFET transistor formed on a substrate and a hetero-bipolar transistor formed within the substrate. The bipolar transistor can be used to inject charge carriers into a floating gate of the MOSFET transistor. This is done by operating the MOSFET transistor to form an inversion layer in its channel region and operating the bipolar transistor to drive minority charge carriers from the substrate into a floating gate of the MOSFET transistor. The substrate provides a silicon emitter and a silicon germanium containing base for the bipolar transistor. The inversion layer provides a silicon collector for the bipolar transistor.

Abstract translation: 异质BiMOS注入系统包括形成在衬底上的MOSFET晶体管和形成在衬底内的异质双极晶体管。 双极晶体管可用于将电荷载流子注入MOSFET晶体管的浮置栅极。 这通过操作MOSFET晶体管在其沟道区域中形成反型层并且操作双极晶体管来驱动少数电荷载体从衬底驱动到MOSFET晶体管的浮置栅极。 衬底为双极晶体管提供硅发射极和含硅锗基底。 反型层为双极晶体管提供硅集电极。