公开(公告)号：US20100327439A1

公开(公告)日：2010-12-30

申请号：US12875551

申请日：2010-09-03

Applicant: Tae-Joo Hwang ,  Tae-Gyeong Chung ,  Eun-Chul Ahn

Inventor： Tae-Joo Hwang ,  Tae-Gyeong Chung ,  Eun-Chul Ahn

IPC: H01L23/485 ,  H01L23/48

CPC classification number: H01L23/49811 ,  H01L23/481 ,  H01L24/06 ,  H01L24/16 ,  H01L24/29 ,  H01L24/31 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/078 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.

Abstract translation: 半导体封装包括第一封装衬底，设置在第一封装衬底上的第一半导体芯片，包括第一通孔通孔的半导体芯片和设置在第一半导体芯片上的芯片封装，芯片封装包括第二封装衬底和 设置在所述第二封装基板上的第二半导体芯片，其中，第一导电端子设置在所述半导体芯片的第一表面上，并且第二导电端子设置在所述第二封装基板的第一表面上，所述第一导电端子设置在所述第二封装基板的第二表面上 导电端子。

公开(公告)号：US07574638B2

公开(公告)日：2009-08-11

申请号：US11345897

申请日：2006-02-02

Applicant: Hae-Jin Song ,  Jin-Tae Joo

Inventor： Hae-Jin Song ,  Jin-Tae Joo

IPC: G01R31/28

CPC classification number: G01R31/3172 ,  G01R31/31723 ,  G01R31/31725

Abstract: The present invention provides semiconductor devices capable of being tested using one test pin and using an input/output pin without any test pins, and methods of testing the same. One semiconductor device comprises a test pin for inputting/outputting test data, an operation mode controller for activating an enable signal in response to an external reset signal and a clock signal, an operation mode storage for receiving serial data synchronized with the clock signal through the test pin in response to the enable signal, and an operation mode decoder for generating operation mode selection signals in response to the serial data stored in the operation mode storage. Another semiconductor device comprises an input/output pin for receiving test data, a delay reset signal generator for delaying a reset signal, a counter for counting a clock signal in response to the reset signal to generate a counted value, a mode register for storing the test data, and a decoder for generating selection signals to the mode register to designate a position in the mode register where the test data is written.

Abstract translation: 本发明提供能够使用一个测试引脚进行测试并且使用没有任何测试引脚的输入/输出引脚的半导体器件及其测试方法。 一个半导体器件包括用于输入/输出测试数据的测试引脚，用于响应于外部复位信号和时钟信号激活使能信号的操作模式控制器，用于通过所述时钟信号接收与时钟信号同步的串行数据的操作模式存储器 测试引脚以及响应于存储在操作模式存储器中的串行数据产生操作模式选择信号的操作模式解码器。 另一个半导体器件包括用于接收测试数据的输入/输出引脚，用于延迟复位信号的延迟复位信号发生器，响应于复位信号计数时钟信号的计数器以产生计数值;模式寄存器， 测试数据和用于向模式寄存器产生选择信号的解码器，以指定写入测试数据的模式寄存器中的位置。

公开(公告)号：US20080277800A1

公开(公告)日：2008-11-13

申请号：US12149741

申请日：2008-05-07

Applicant: Tae-Joo Hwang ,  Tae-Gyeong Chung ,  Eun-Chul Ahn

Inventor： Tae-Joo Hwang ,  Tae-Gyeong Chung ,  Eun-Chul Ahn

IPC: H01L23/538 ,  H01L21/60

CPC classification number: H01L23/481 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/97 ,  H01L25/03 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Example embodiments relate to semiconductor packages and methods of forming the same. A semiconductor package according to example embodiments may include a printed circuit board (PCB), a first semiconductor chip mounted on the PCB, and a chip package mounted on the first semiconductor chip. The chip package may be in direct contact with the first semiconductor chip.

Abstract translation: 示例性实施例涉及半导体封装及其形成方法。 根据示例实施例的半导体封装可以包括印刷电路板（PCB），安装在PCB上的第一半导体芯片和安装在第一半导体芯片上的芯片封装。 芯片封装可以与第一半导体芯片直接接触。

公开(公告)号：US20080122084A1

公开(公告)日：2008-05-29

申请号：US11946750

申请日：2007-11-28

Applicant: Tae-Joo HWANG ,  Eun-Chul AHN ,  Tae-Gyeong CHUNG

Inventor： Tae-Joo HWANG ,  Eun-Chul AHN ,  Tae-Gyeong CHUNG

IPC: H01L23/48 ,  H01L21/58

CPC classification number: H01L24/90 ,  H01L23/3171 ,  H01L24/83 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/274 ,  H01L2224/32225 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A flip-chip assembly comprises a semiconductor chip, a substrate, a first buffer layer, a second buffer layer and a conductive bump. The semiconductor chip includes a first region and a second region adjacent to the first region. The substrate is disposed under the semiconductor chip. The first buffer layer is disposed between the first region of the semiconductor chip and the substrate. The second buffer layer is disposed between the second region of the semiconductor chip and the substrate. The conductive bump is formed through the second buffer layer and electrically connects the semiconductor chip to the substrate.

Abstract translation: 倒装芯片组件包括半导体芯片，衬底，第一缓冲层，第二缓冲层和导电凸块。 半导体芯片包括与第一区域相邻的第一区域和第二区域。 衬底设置在半导体芯片下方。 第一缓冲层设置在半导体芯片的第一区域和基板之间。 第二缓冲层设置在半导体芯片的第二区域和基板之间。 导电凸块通过第二缓冲层形成并将半导体芯片电连接到基板。

公开(公告)号：US20080112560A1

公开(公告)日：2008-05-15

申请号：US11923806

申请日：2007-10-25

Applicant: Bon Seok KOO ,  Gwon Ho RYU ,  Sang Woon YANG ,  Tae Joo CHANG

Inventor： Bon Seok KOO ,  Gwon Ho RYU ,  Sang Woon YANG ,  Tae Joo CHANG

IPC: H04L9/06

CPC classification number: H04L9/0631 ,  H04L2209/122

Abstract: Provided are an arithmetic method and apparatus for supporting Advanced Encryption Standard (AES) and Academy, Research Institute and Agency (ARIA) encryption/decryption functions. The apparatus includes: a key scheduler for generating a round key using an input key; and a round function calculator for generating encrypted/decrypted data using input data and the round key. Here, the round function calculator includes an integrated substitution layer and an integrated diffusion layer capable of performing both AES and ARIA algorithms.

Abstract translation: 提供了用于支持高级加密标准（AES）和Academy，Research Institute and Agency（ARIA）加密/解密功能的算术方法和装置。 该装置包括：密钥调度器，用于使用输入密钥生成圆键; 以及循环函数计算器，用于使用输入数据和所述循环密钥来生成加密/解密数据。 这里，循环函数计算器包括集成替代层和能够执行AES和ARIA算法的集成扩散层。

公开(公告)号：US06757026B2

公开(公告)日：2004-06-29

申请号：US09841252

申请日：2001-04-25

Applicant: Jin-Tae Joo

Inventor： Jin-Tae Joo

IPC: H04N701

CPC classification number: H04N7/0135 ,  G06T3/4007 ,  G09G5/00 ,  G09G5/02 ,  G09G2340/0414 ,  G09G2340/0421 ,  H04N5/14 ,  H04N9/64 ,  H04N9/642

Abstract: An apparatus for converting image format and methods thereof in a video signal processing system. The apparatus includes an analog-to-digital converting unit for sampling original color signals at predetermined intervals and converting the sampled signals into digital signals; a color-space converting unit for converting a digital signal of the analog-to-digital converting unit into a brightness signal and a color tone signal and for outputting these signals; a storage unit for storing a look-up table representing linear interpolation coefficients converted in response to a conversion of an image size; a horizontal scaling unit for linearly interpolating one cycle of the brightness signal and color tone signal in response to a conversion of image size with reference to the look-up table of the storage unit, and for horizontally scaling by repeatedly outputting the outcome linearly-interpolated; a line memory unit for momentarily storing a horizontally scaled signal by the horizontal scaling unit; a vertical scaling unit for interpolating a cycle of a horizontal scaling signal provided by the line memory unit in response to the conversion of the image size with reference to the look-up table, thereby vertically scaling by repeatedly outputting the linearly interpolated data; and a frame memory unit for storing signals vertically and horizontally-scaled by the vertical scaling unit and for converting vertical and horizontal frequencies of the vertical and horizontal scaled signals.

Abstract translation: 一种用于在视频信号处理系统中转换图像格式及其方法的装置。 该装置包括用于以预定间隔对原始颜色信号进行采样并将采样信号转换为数字信号的模数转换单元; 色空间转换单元，用于将模数转换单元的数字信号转换成亮度信号和色调信号并输出​​这些信号; 存储单元，用于存储表示响应于图像大小的转换而转换的线性内插系数的查找表; 水平缩放单元，用于响应于参考存储单元的查找表的图像尺寸的转换来线性内插亮度信号和色调信号的一个周期，并且通过重复地输出线性内插的结果来水平缩放 ; 行存储单元，用于通过水平缩放单元暂时存储水平缩放信号; 垂直缩放单元，用于响应于参考查找表的图像大小的转换来内插由行存储器单元提供的水平缩放信号的周期，从而通过重复输出线性内插数据进行垂直缩放; 以及帧存储单元，用于存储由垂直缩放单元垂直和水平缩放的信号，并用于转换垂直和水平缩放信号的垂直和水平频率。