公开(公告)号：US09405547B2

公开(公告)日：2016-08-02

申请号：US13082146

申请日：2011-04-07

申请人： Cheng Wang ,  Youfeng Wu

发明人： Cheng Wang ,  Youfeng Wu

IPC分类号： G06F9/38

CPC分类号： G06F9/3842 ,  G06F9/3838 ,  G06F9/384

摘要： A system may comprise an optimizer/scheduler to schedule on a set of instructions, compute a data dependence, a checking constraint and/or an anti-checking constraint for the set of scheduled instructions, and allocate alias registers for the set of scheduled instructions based on the data dependence, the checking constraint and/or the anti-checking constraint. In one embodiment, the optimizer is to release unused registers to reduce the alias registers used to protect the scheduled instructions. The optimizer is further to insert a dummy instruction after a fused instruction to break cycles in the checking and anti-checking constraints.

摘要翻译： 系统可以包括优化器/调度器，以对一组指令进行调度，计算数据依赖性，检查约束和/或针对所安排的指令集合的反检查约束，并且为该组调度指令分配别名寄存器 关于数据依赖性，检查约束和/或反检查约束。 在一个实施例中，优化器是释放未使用的寄存器以减少用于保护调度指令的别名寄存器。 优化器进一步在融合指令之后插入一个虚拟指令，以便在检查和反查约束中打破周期。

公开(公告)号：US20160116965A1

公开(公告)日：2016-04-28

申请号：US14986678

申请日：2016-01-02

申请人： Youfeng Wu ,  Shiliang Hu ,  Edson Borin ,  Cheng Wang

发明人： Youfeng Wu ,  Shiliang Hu ,  Edson Borin ,  Cheng Wang

IPC分类号： G06F1/32 ,  G06F9/50

CPC分类号： G06F1/329 ,  G06F1/3287 ,  G06F9/3851 ,  G06F9/445 ,  G06F9/4893 ,  G06F9/5027 ,  G06F9/5094 ,  G06F11/3409 ,  G06F11/3452 ,  G06F11/3466 ,  G06F2201/81 ,  G06F2201/865 ,  G06F2201/88 ,  G06F2209/501 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D10/34 ,  Y02D50/20

摘要： Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

公开(公告)号：US20160092234A1

公开(公告)日：2016-03-31

申请号：US14497833

申请日：2014-09-26

申请人： NALINI VASUDEVAN ,  CHENG WANG ,  YOUFENG WU ,  ALBERT HARTONO ,  SARA S. BAGHSORKHI

发明人： NALINI VASUDEVAN ,  CHENG WANG ,  YOUFENG WU ,  ALBERT HARTONO ,  SARA S. BAGHSORKHI

IPC分类号： G06F9/38

CPC分类号： G06F9/3842 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/3013 ,  G06F9/30174 ,  G06F9/3824 ,  G06F9/3834 ,  G06F9/3838 ,  G06F15/8053

摘要： An apparatus and method for speculative vectorization. For example, one embodiment of a processor comprises: a queue comprising a set of locations for storing addresses associated with vectorized memory access instructions; and execution logic to execute a first vectorized memory access instruction to access the queue and to compare a new address associated with the first vectorized memory access instruction with existing addresses stored within a specified range of locations within the queue to detect whether a conflict exists, the existing addresses having been previously stored responsive to one or more prior vectorized memory access instructions.

摘要翻译： 一种用于推测矢量化的装置和方法。 例如，处理器的一个实施例包括：队列，其包括用于存储与向量化存储器访问指令相关联的地址的一组位置; 以及执行逻辑，以执行第一向量化存储器访问指令以访问队列，并将与第一向量化存储器访问指令相关联的新地址与存储在队列内的指定范围内的现有地址进行比较，以检测冲突是否存在， 先前已存储的存储的地址响应于一个或多个先前的向量化存储器访问指令而被存储。

公开(公告)号：US20150212836A1

公开(公告)日：2015-07-30

申请号：US14126894

申请日：2013-10-24

申请人： Hongbo Rong ,  Hyunchul Park ,  Cheng Wang ,  Youfeng Wu

发明人： Hongbo Rong ,  Hyunchul Park ,  Cheng Wang ,  Youfeng Wu

IPC分类号： G06F9/455 ,  G06F9/45

CPC分类号： G06F9/4552 ,  G06F8/4442 ,  G06F8/52 ,  G06F9/45508 ,  G06F9/45533

摘要： Methods and apparatus relating to conjugate code generation for efficient dynamic optimizations are described. In an embodiment, a binary code and an intermediate representation (IR) code are generated based at least partially on a source program. The binary code and the intermediate code are transmitted to a virtual machine logic. The binary code and the IR code each include a plurality of regions that are in one-to-one correspondence. Other embodiments are also claimed and described.

摘要翻译： 描述了用于有效动态优化的共轭码生成相关的方法和装置。 在一个实施例中，至少部分地基于源程序生成二进制代码和中间表示（IR）代码。 二进制代码和中间代码被传送到虚拟机逻辑。 二进制代码和IR代码每个包括一对一对应的多个区域。 还要求保护和描述其它实施例。

公开(公告)号：US20150169226A1

公开(公告)日：2015-06-18

申请号：US14496621

申请日：2014-09-25

申请人： Xipeng Shen ,  Youfeng Wu ,  Cheng Wang ,  Hyunchul Park ,  Hongbo Rong

发明人： Xipeng Shen ,  Youfeng Wu ,  Cheng Wang ,  Hyunchul Park ,  Hongbo Rong

IPC分类号： G06F3/06

CPC分类号： G06F12/0238 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7207

摘要： Technologies for persistent memory programming include a computing device having a persistent memory including one or more nonvolatile regions. The computing device may assign a virtual memory address of a target location in persistent memory to a persistent memory pointer using persistent pointer strategy, and may dereference the pointer using the same strategy. Persistent pointer strategies include off-holder, ID-in-value, optimistic rectification, and pessimistic rectification. The computing device may log changes to persistent memory during the execution of a data consistency section, and commit changes to the persistent memory when the last data consistency section ends. Data consistency sections may be grouped by log group identifier. Using type metadata stored in the nonvolatile region, the computing device may identify the type of a root object within the nonvolatile region and then recursively identify the type of all objects referenced by the root object. Other embodiments are described and claimed.

摘要翻译： 用于持久存储器编程的技术包括具有包括一个或多个非易失性区域的持久存储器的计算设备。 计算设备可以使用持久指针策略将永久存储器中的目标位置的虚拟存储器地址分配给持久存储器指针，并且可以使用相同的策略来解除引用。 持续指标策略包括持有人，价值观，乐观整改和悲观整改。 在执行数据一致性部分期间，计算设备可以将改变记录到持久存储器，并且当最后数据一致性部分结束时，向永久存储器提交更改。 数据一致性部分可以按日志组标识符分组。 使用存储在非易失性区域中的类型元数据，计算设备可以识别非易失性区域内的根对象的类型，然后递归地标识由根对象引用的所有对象的类型。 描述和要求保护其他实施例。

公开(公告)号：US08789031B2

公开(公告)日：2014-07-22

申请号：US11901644

申请日：2007-09-18

申请人： Wei Liu ,  Lixin Su ,  Youfeng Wu ,  Herbert Hum

发明人： Wei Liu ,  Lixin Su ,  Youfeng Wu ,  Herbert Hum

IPC分类号： G06F9/45

CPC分类号： G06F8/433

摘要： In one embodiment, the present invention includes a software-controlled method of forming instruction strands. The software may include instructions to obtain code of a superblock including a plurality of basic blocks, build a dependency directed acyclic graph (DAG) for the code, sort nodes coupled by edges of the dependency DAG into a topological order, form strands from the nodes based on hardware constraints, rule constraints, and scheduling constraints, and generate executable code for the strands and store the executable code in a storage. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括一种形成指令串的软件控制方法。 软件可以包括用于获得包括多个基本块的超级块的代码的指令，为代码构建依赖性有向非循环图（DAG），将依赖性DAG的边缘耦合的分类节点排列成拓扑顺序，从节点形成线 基于硬件约束，规则约束和调度约束，并且生成链的可执行代码并将可执行代码存储在存储器中。 描述和要求保护其他实施例。

公开(公告)号：US20140007054A1

公开(公告)日：2014-01-02

申请号：US13535334

申请日：2012-06-27

申请人： Youfeng Wu ,  Justin E. Gottschlich ,  Gilles Pokam ,  Shiliang Hu ,  Ali-Reza Adl-Tabatabai ,  Cristiano L. Pereira

发明人： Youfeng Wu ,  Justin E. Gottschlich ,  Gilles Pokam ,  Shiliang Hu ,  Ali-Reza Adl-Tabatabai ,  Cristiano L. Pereira

IPC分类号： G06F11/36

CPC分类号： G06F11/3688 ,  G06F8/70 ,  G06F11/36 ,  G06F11/3632

摘要： Methods and systems to identify and reproduce concurrency bugs in multi-threaded programs are disclosed. An example method disclosed herein includes defining a data type. The data type includes a first predicate associated with a first thread of a multi-threaded program that is associated with a first condition, a second predicate that is associated with a second thread of the multi-threaded program, the second predicate being associated with a second condition, and an expression that defines a relationship between the first predicate and the second predicate. The relationship, when satisfied, causes the concurrency bug to be detected. A concurrency bug detector conforming to the data type is used to detect the concurrency bug in the multi-threaded program.

摘要翻译： 公开了在多线程程序中识别和再现并发错误的方法和系统。 本文公开的示例性方法包括定义数据类型。 数据类型包括与第一条件相关联的多线程程序的第一线程相关联的第一谓词，与多线程程序的第二线程相关联的第二谓词，第二谓词与第一谓词相关联 第二个条件和一个定义第一个谓词和第二个谓词之间的关系的表达式。 这种关系在满足时会导致并发错误被检测到。 符合数据类型的并发错误检测器用于检测多线程程序中的并发错误。

公开(公告)号：US08549267B2

公开(公告)日：2013-10-01

申请号：US12644151

申请日：2009-12-22

申请人： Edson Borin ,  Youfeng Wu

发明人： Edson Borin ,  Youfeng Wu

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC分类号： G06F9/30145 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3863

摘要： Example methods and apparatus to manage partial commit-checkpoints are disclosed. A disclosed example method includes identifying a commit instruction associated with a region of instructions executed by a processor, identifying candidate instructions from the region of instructions, and generating a processor partial commit-checkpoint to save a current state of the processor, the checkpoint based on calculated register values associated with live instructions, and including instruction reference addresses to link the candidate instructions.

摘要翻译： 公开了用于管理部分提交检查点的示例性方法和装置。 所公开的示例性方法包括识别与由处理器执行的指令区域相关联的提交指令，从指令区域识别候选指令，以及生成处理器部分提交检查点以保存处理器的当前状态，所述检查点基于 与实时指令相关联的计算寄存器值，并包括链接候选指令的指令参考地址。

公开(公告)号：US08443353B2

公开(公告)日：2013-05-14

申请号：US12890639

申请日：2010-09-25

申请人： Mauricio Breternitz, Jr. ,  Youfeng Wu ,  Cheng Wang ,  Edson Borin ,  Shiliang Hu ,  Craig B. Zilles

发明人： Mauricio Breternitz, Jr. ,  Youfeng Wu ,  Cheng Wang ,  Edson Borin ,  Shiliang Hu ,  Craig B. Zilles

IPC分类号： G06F9/45

摘要： An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.

公开(公告)号：US20120260072A1

公开(公告)日：2012-10-11

申请号：US13082146

申请日：2011-04-07

申请人： Cheng Wang ,  Youfeng Wu

发明人： Cheng Wang ,  Youfeng Wu

IPC分类号： G06F9/30

CPC分类号： G06F9/3842 ,  G06F9/3838 ,  G06F9/384

摘要： A system may comprises an optimizer/scheduler to schedule on a set of instructions, compute a data dependence, a checking constraint and/or an anti-checking constraint for the set of scheduled instructions, and allocate alias registers for the set of scheduled instructions based on the data dependence, the checking constraint and/or the anti-checking constraint. In one embodiment, the optimizer is to release unused registers to reduce the alias registers used to protect the scheduled instructions. The optimizer is further to insert a dummy instruction after a fused instruction to break cycles in the checking and anti-checking constraints.

摘要翻译： 系统可以包括优化器/调度器，以在一组指令上调度，计算数据依赖性，检查约束和/或针对所设置的指令集合的反检查约束，并且为该组调度指令分配别名寄存器 关于数据依赖性，检查约束和/或反检查约束。 在一个实施例中，优化器是释放未使用的寄存器以减少用于保护调度指令的别名寄存器。 优化器进一步在融合指令之后插入一个虚拟指令，以便在检查和反查约束中打破周期。