公开(公告)号：US08187935B2

公开(公告)日：2012-05-29

申请号：US12795025

申请日：2010-06-07

Applicant: Young-Ho Lee ,  Keon-Soo Kim ,  Jae-Hwang Sim ,  Jin-Hyun Shin ,  Kyung-Hoon Min

Inventor： Young-Ho Lee ,  Keon-Soo Kim ,  Jae-Hwang Sim ,  Jin-Hyun Shin ,  Kyung-Hoon Min

IPC: H01L21/8247

CPC classification number: H01L21/76229 ,  H01L21/823481 ,  H01L27/1052

Abstract: A method of forming an active region structure includes preparing a semiconductor substrate having a cell array region and a peripheral circuit region, forming upper cell mask patterns having a line shape in the cell array region, forming first and second peripheral mask patterns in the peripheral circuit region, the first and second peripheral mask patterns being stacked in sequence and covering the peripheral circuit region, and upper surfaces of the upper cell mask patterns forming a step difference with an upper surface of the second peripheral mask pattern, forming spacers on sidewalls of the upper cell mask patterns to expose lower portions of the upper cell mask patterns and the second peripheral mask pattern, and removing the lower portions of the upper cell mask patterns using the spacers and the first and second peripheral mask patterns as an etch mask.

Abstract translation: 形成有源区域结构的方法包括制备具有单元阵列区域和外围电路区域的半导体衬底，在单元阵列区域中形成具有线状的上层单元掩模图案，在外围电路中形成第一和第二外围掩模图案 区域，第一外围掩模图案和第二外围掩模图案依次堆叠并覆盖外围电路区域，并且上部单元掩模图案的上表面与第二外围掩模图案的上表面形成阶梯差，在第二外围掩模图案的侧壁上形成间隔物 上部单元掩模图案以暴露上部单元掩模图案和第二外围掩模图案的下部，并且使用间隔件和第一外围掩模图案和第二外围掩模图案作为蚀刻掩模去除上部单元掩模图案的下部。

公开(公告)号：US20110227231A1

公开(公告)日：2011-09-22

申请号：US13111100

申请日：2011-05-19

Applicant: Young-Ho Lee ,  Jae-Hwang Sim ,  Jae-Kwan Park ,  Mo-Seok Kim ,  Jong-Min Lee ,  Dong-Sik Lee

Inventor： Young-Ho Lee ,  Jae-Hwang Sim ,  Jae-Kwan Park ,  Mo-Seok Kim ,  Jong-Min Lee ,  Dong-Sik Lee

IPC: H01L23/48

CPC classification number: H01L21/76816 ,  H01L21/31144

Abstract: A semiconductor device may include plugs disposed in a zigzag pattern, interconnections electrically connected to the plugs and a protection pattern which is interposed between the plugs and the interconnections to selectively expose the plugs. The interconnections may include a connection portion which is in contact with plugs selectively exposed by the protection pattern. A method of manufacturing a semiconductor device includes, after forming a molding pattern and a mask pattern, selectively etching a protection layer using the mask pattern to form a protection pattern exposing a plug.

Abstract translation: 半导体器件可以包括以锯齿形图案布置的插塞，电连接到插头的互连和插入在插头和互连之间的保护图案以选择性地暴露插头。 互连可以包括与由保护图案选择性地暴露的插头接触的连接部分。 制造半导体器件的方法包括：在形成模制图案和掩模图案之后，使用掩模图案选择性地蚀刻保护层以形成露出插头的保护图案。

公开(公告)号：US07968447B2

公开(公告)日：2011-06-28

申请号：US12465013

申请日：2009-05-13

Applicant: Young-Ho Lee ,  Jae-Hwang Sim ,  Jae-Kwan Park ,  Mo-Seok Kim ,  Jong-Min Lee ,  Dong-Sik Lee

Inventor： Young-Ho Lee ,  Jae-Hwang Sim ,  Jae-Kwan Park ,  Mo-Seok Kim ,  Jong-Min Lee ,  Dong-Sik Lee

IPC: H01L21/4763

CPC classification number: H01L21/76816 ,  H01L21/31144

Abstract: A semiconductor device may include plugs disposed in a zigzag pattern, interconnections electrically connected to the plugs and a protection pattern which is interposed between the plugs and the interconnections to selectively expose the plugs. The interconnections may include a connection portion which is in contact with plugs selectively exposed by the protection pattern. A method of manufacturing a semiconductor device includes, after forming a molding pattern and a mask pattern, selectively etching a protection layer using the mask pattern to form a protection pattern exposing a plug.

Abstract translation: 半导体器件可以包括以锯齿形图案布置的插塞，电连接到插头的互连和插入在插头和互连之间的保护图案以选择性地暴露插头。 互连可以包括与由保护图案选择性地暴露的插头接触的连接部分。 制造半导体器件的方法包括：在形成模制图案和掩模图案之后，使用掩模图案选择性地蚀刻保护层以形成露出插头的保护图案。

公开(公告)号：US20110073940A1

公开(公告)日：2011-03-31

申请号：US12649999

申请日：2009-12-30

Applicant: Jin-Ku LEE ,  Young-Ho Lee ,  Mi-Ri Lee

Inventor： Jin-Ku LEE ,  Young-Ho Lee ,  Mi-Ri Lee

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7845 ,  H01L21/28518 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7856

Abstract: A method for fabricating a semiconductor device includes forming a first conductive layer doped with an impurity for forming a cell junction over a semiconductor substrate, forming a second conductive layer over the first conductive layer, forming a plurality of active regions by etching the second conductive layer and the first conductive layer, the plurality of the active regions being separated from one another by trenches, forming a side contact connected to a sidewall of the first conductive layer, and forming a plurality of metal bit lines each connected to the side contact and filling a portion of each trench.

Abstract translation: 一种制造半导体器件的方法包括：在半导体衬底上形成掺杂有用于形成电池结的杂质的第一导电层，在第一导电层上形成第二导电层，通过蚀刻第二导电层形成多个有源区 和所述第一导电层，所述多个有源区域通过沟槽彼此分开，形成连接到所述第一导电层的侧壁的侧面接触，以及形成多个金属位线，每个金属位线连接到所述侧面接触和填充 每个沟槽的一部分。

公开(公告)号：US20110001576A1

公开(公告)日：2011-01-06

申请号：US12497601

申请日：2009-07-03

Applicant: Young Ho Lee ,  Sun Young Lee ,  Young Kwon

Inventor： Young Ho Lee ,  Sun Young Lee ,  Young Kwon

IPC: H01P5/18

CPC classification number: H01P5/187

Abstract: A power amplifier module comprises a power amplifier disposed in a coreless substrate and a directional coupler disposed in a coreless substrate and connected to the power amplifier.

Abstract translation: 功率放大器模块包括设置在无芯基板中的功率放大器和布置在无芯基板中并连接到功率放大器的定向耦合器。

公开(公告)号：US20100128835A1

公开(公告)日：2010-05-27

申请号：US12420874

申请日：2009-04-09

Applicant: Kyung Ho Yoon ,  Jae Yong Kim ,  Young Ho Lee ,  Kun Woo Song ,  Tae Hyun Chun ,  Dong Seok Oh ,  Wang Ki In ,  Hyung Kyu Kim ,  Chang Hwan Shin ,  Kang Hee Lee

Inventor： Kyung Ho Yoon ,  Jae Yong Kim ,  Young Ho Lee ,  Kun Woo Song ,  Tae Hyun Chun ,  Dong Seok Oh ,  Wang Ki In ,  Hyung Kyu Kim ,  Chang Hwan Shin ,  Kang Hee Lee

IPC: G21C3/30

CPC classification number: G21C3/322 ,  G21C3/33 ,  Y02E30/38

Abstract: An intermediate end plug assembly for a segmented fuel rod can stably support the fuel rod to the end of its cycle even if an interval between the fuel rods becomes narrow due to application of a dual-cooled fuel rod, and reduce excess vibration induced by flows of interior and exterior channels of the dual-cooled fuel rod for obtaining high burnup and output. To this end, the fuel rod has a segmented structure so as to make its length short. A lower intermediate end plug includes at least one channel hole, through which a coolant flows into an internal channel of the fuel rod, so that a possibility of causing departure from nuclear boiling ratio (DNBR) of the dual-cooled fuel rod is reduced.

Abstract translation: 用于分段燃料棒的中间端塞组件即使燃料棒之间的间隔由于施加双重冷却燃料棒而变窄，也可以稳定地将燃料棒支撑到其循环结束，并减少由流动引起的过量振动 的双冷却燃料棒的内部和外部通道，以获得高燃耗和输出。 为此，燃料棒具有分段结构以使其长度短。 下部中间端塞包括至少一个通道孔，冷却剂通过该通道孔流入燃料棒的内部通道，从而降低了双重冷却燃料棒的核沸腾比（DNBR）的可能性。

公开(公告)号：US20100096719A1

公开(公告)日：2010-04-22

申请号：US12418023

申请日：2009-04-03

Applicant: Young-Ho Lee ,  Jae-Kwan Park ,  Jae-Hwang Sim ,  Sang-Yong Park

Inventor： Young-Ho Lee ,  Jae-Kwan Park ,  Jae-Hwang Sim ,  Sang-Yong Park

IPC: H01L29/06 ,  H01L21/762 ,  H01L23/544

CPC classification number: H01L27/0207 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/76229 ,  H01L23/544 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

Abstract: A method of fabricating an integrated circuit device includes forming first and second mask structures on respective first and second regions of a feature layer. Each of the first and second mask structures includes a dual mask pattern and an etch mask pattern thereon having an etch selectivity relative to the dual mask pattern. The etch mask patterns of the first and second mask structures are isotropically etched to remove the etch mask pattern from the first mask structure while maintaining at least a portion of the etch mask pattern on the second mask structure. Spacers are formed on opposing sidewalls of the first and second mask structures. The first mask structure is selectively removed from between the spacers in the first region using the portion of the etch mask pattern on the second mask structure as a mask to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region, and a second mask pattern including the opposing sidewall spacers with the second mask structure therebetween in the second region. The feature layer may be patterned using the first mask pattern as a mask to define a first feature on the first region, and using the second mask pattern as a mask to define a second feature on the second region having a greater width than the first feature.

Abstract translation: 制造集成电路器件的方法包括在特征层的相应的第一和第二区域上形成第一和第二掩模结构。 第一和第二掩模结构中的每一个包括双掩模图案和其上具有相对于双掩模图案的蚀刻选择性的蚀刻掩模图案。 各向同性蚀刻第一和第二掩模结构的蚀刻掩模图案以从第一掩模结构去除蚀刻掩模图案，同时将蚀刻掩模图案的至少一部分保持在第二掩模结构上。 间隔件形成在第一和第二掩模结构的相对侧壁上。 使用第二掩模结构上的蚀刻掩模图案的部分作为掩模，第一掩模结构从第一区域中的间隔物之间​​选择性地移除，以限定第一掩模图案，其包括在第一区域中具有空隙的相对的侧壁间隔物 以及第二掩模图案，其包括在第二区域中具有第二掩模结构的相对的侧壁间隔物。 可以使用第一掩模图案作为掩模来对特征层进行图案化，以在第一区域上限定第一特征，并且使用第二掩模图案作为掩模来限定具有比第一特征宽的宽度的第二区域上的第二特征 。

公开(公告)号：US20090310058A1

公开(公告)日：2009-12-17

申请号：US12466601

申请日：2009-05-15

Applicant: Yong-ll Kim ,  Hyun-Su Park ,  Young-Ho Lee ,  Jae-Hwan Chun ,  Sung-Won Chung

Inventor： Yong-ll Kim ,  Hyun-Su Park ,  Young-Ho Lee ,  Jae-Hwan Chun ,  Sung-Won Chung

IPC: G02F1/1333 ,  F21V15/00 ,  H01J9/00

CPC classification number: G02F1/133604 ,  G02F1/133608 ,  G02F2001/133612

Abstract: A backlight assembly includes a lamp socket unit, a printed circuit board and a lower receiving container. The printed circuit board includes a cutout portion which receives the lamp socket unit therethrough. The lower receiving container receives the lamp socket unit and the printed circuit board. The lamp socket unit is coupled to the printed circuit board, and the printed circuit board, having the lamp socket unit coupled thereto, is disposed in the lower receiving container.

Abstract translation: 背光组件包括灯座单元，印刷电路板和下接收容器。 印刷电路板包括通过其接收灯座单元的切口部分。 下接收容器接收灯座单元和印刷电路板。 灯座单元耦合到印刷电路板，并且具有与其连接的灯座单元的印刷电路板设置在下容纳容器中。

公开(公告)号：US07605070B2

公开(公告)日：2009-10-20

申请号：US11154474

申请日：2005-06-17

Applicant: Young-Ho Lee

Inventor： Young-Ho Lee

IPC: H01L21/20

CPC classification number: H01L21/76897 ,  H01L21/02063 ,  H01L21/28525 ,  H01L21/76877

Abstract: Disclosed are a contact plug of a semiconductor device and a method for fabricating the same. The semiconductor device includes: an epitaxial stack formed by inserting a heteroepitaxy layer between a pair of homoepitaxy layers; and a contact plug including a metal layer on the epitaxial stack. Accordingly, in accordance with the present invention, the contact plug is selectively doped in a high concentration, thereby reducing a contact resistance. Furthermore, the present invention also provides an effect of reducing degradation in a device property without decreasing yields of products by minimizing a thermal budget through using a SEG-silicon germanium layer capable of obtaining a high doping concentration and a high deposition speed.

Abstract translation: 公开了半导体器件的接触插头及其制造方法。 半导体器件包括：通过在一对同质外延层之间插入异质外延层而形成的外延堆叠; 以及包括外延层上的金属层的接触插塞。 因此，根据本发明，以高浓度选择性地掺杂接触插塞，从而降低接触电阻。 此外，本发明还提供了通过使用能够获得高掺杂浓度和高沉积速度的SEG硅锗层，通过最小化热预算来降低器件特性降低而不降低产品产量的效果。

公开(公告)号：US20090154212A1

公开(公告)日：2009-06-18

申请号：US12292700

申请日：2008-11-24

Applicant: Sung-Joo Park ,  Kyoung-Sun Kim ,  Young-Ho Lee ,  Jea-Eun Lee

Inventor： Sung-Joo Park ,  Kyoung-Sun Kim ,  Young-Ho Lee ,  Jea-Eun Lee

IPC: G11C5/02 ,  G11C5/06 ,  G11C7/00

CPC classification number: G11C7/20 ,  G11C5/04 ,  G11C5/066 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1093 ,  G11C2207/105

Abstract: A memory module, includes a memory module board and a plurality of memory devices on the memory module board. The memory module board includes one or more first input terminals configured to receive first signals to individually control the memory devices, and one or more second input terminals configured to receive second signals to commonly control the memory devices. Each of the memory devices includes a plurality of first signal input units configured to receive the first signals through one or more first input pins, a plurality of second signal input units configured to receive the second signals through one or more second input pins, and a plurality of dummy units, the dummy units being respectively connected to the first signal input units in parallel, and being configured to receive the first signals through one or more third input pins and to compensate for a signal line load.

Abstract translation: 存储器模块包括存储器模块板和存储器模块板上的多个存储器件。 存储器模块板包括被配置为接收第一信号以单独控制存储器件的一个或多个第一输入端子，以及被配置为接收第二信号以共同控制存储器件的一个或多个第二输入端子。 每个存储器件包括多个第一信号输入单元，其被配置为通过一个或多个第一输入引脚接收第一信号;多个第二信号输入单元，被配置为通过一个或多个第二输入引脚接收第二信号;以及 多个虚拟单元，虚拟单元分别并联连接到第一信号输入单元，并且被配置为通过一个或多个第三输入引脚接收第一信号并补偿信号线负载。