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    Memory module
    1.
    发明申请
    Memory module 有权
    内存模块

    公开(公告)号：US20090154212A1

    公开(公告)日：2009-06-18

    申请号：US12292700

    申请日：2008-11-24

    申请人： Sung-Joo Park ,  Kyoung-Sun Kim ,  Young-Ho Lee ,  Jea-Eun Lee

    发明人： Sung-Joo Park ,  Kyoung-Sun Kim ,  Young-Ho Lee ,  Jea-Eun Lee

    IPC分类号： G11C5/02 ,  G11C5/06 ,  G11C7/00

    CPC分类号： G11C7/20 ,  G11C5/04 ,  G11C5/066 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1093 ,  G11C2207/105

    摘要： A memory module, includes a memory module board and a plurality of memory devices on the memory module board. The memory module board includes one or more first input terminals configured to receive first signals to individually control the memory devices, and one or more second input terminals configured to receive second signals to commonly control the memory devices. Each of the memory devices includes a plurality of first signal input units configured to receive the first signals through one or more first input pins, a plurality of second signal input units configured to receive the second signals through one or more second input pins, and a plurality of dummy units, the dummy units being respectively connected to the first signal input units in parallel, and being configured to receive the first signals through one or more third input pins and to compensate for a signal line load.

    摘要翻译： 存储器模块包括存储器模块板和存储器模块板上的多个存储器件。 存储器模块板包括被配置为接收第一信号以单独控制存储器件的一个或多个第一输入端子，以及被配置为接收第二信号以共同控制存储器件的一个或多个第二输入端子。 每个存储器件包括多个第一信号输入单元，其被配置为通过一个或多个第一输入引脚接收第一信号;多个第二信号输入单元，被配置为通过一个或多个第二输入引脚接收第二信号;以及 多个虚拟单元，虚拟单元分别并联连接到第一信号输入单元，并且被配置为通过一个或多个第三输入引脚接收第一信号并补偿信号线负载。

    Memory module
    2.
    发明授权
    Memory module 有权
    内存模块

    公开(公告)号：US07859879B2

    公开(公告)日：2010-12-28

    申请号：US12292700

    申请日：2008-11-24

    申请人： Sung-Joo Park ,  Kyoung-Sun Kim ,  Young-Ho Lee ,  Jea-Eun Lee

    发明人： Sung-Joo Park ,  Kyoung-Sun Kim ,  Young-Ho Lee ,  Jea-Eun Lee

    IPC分类号： G11C5/00

    CPC分类号： G11C7/20 ,  G11C5/04 ,  G11C5/066 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1093 ,  G11C2207/105

    摘要： A memory module, includes a memory module board and a plurality of memory devices on the memory module board. The memory module board includes one or more first input terminals configured to receive first signals to individually control the memory devices, and one or more second input terminals configured to receive second signals to commonly control the memory devices. Each of the memory devices includes a plurality of first signal input units configured to receive the first signals through one or more first input pins, a plurality of second signal input units configured to receive the second signals through one or more second input pins, and a plurality of dummy units, the dummy units being respectively connected to the first signal input units in parallel, and being configured to receive the first signals through one or more third input pins and to compensate for a signal line load.

    摘要翻译： 存储器模块包括存储器模块板和存储器模块板上的多个存储器件。 存储器模块板包括被配置为接收第一信号以单独控制存储器件的一个或多个第一输入端子，以及被配置为接收第二信号以共同控制存储器件的一个或多个第二输入端子。 每个存储器件包括多个第一信号输入单元，其被配置为通过一个或多个第一输入引脚接收第一信号;多个第二信号输入单元，被配置为通过一个或多个第二输入引脚接收第二信号;以及 多个虚拟单元，虚拟单元分别并联连接到第一信号输入单元，并且被配置为通过一个或多个第三输入引脚接收第一信号并补偿信号线负载。

    Methods of forming fine patterns in integrated circuit devices
    5.
    发明授权
    Methods of forming fine patterns in integrated circuit devices 有权
    在集成电路器件中形成精细图案的方法

    公开(公告)号：US09117654B2

    公开(公告)日：2015-08-25

    申请号：US13470773

    申请日：2012-05-14

    申请人： Young-Ho Lee ,  Jae-Kwan Park ,  Jae-Hwang Sim ,  Sang-Yong Park

    发明人： Young-Ho Lee ,  Jae-Kwan Park ,  Jae-Hwang Sim ,  Sang-Yong Park

    IPC分类号： H01L21/467 ,  H01L27/02 ,  H01L21/033 ,  H01L21/308 ,  H01L21/3213 ,  H01L21/762 ,  H01L23/544 ,  H01L27/115 ,  H01L27/105

    CPC分类号： H01L27/0207 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/76229 ,  H01L23/544 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

    摘要： A method of fabricating an integrated circuit device includes forming first and second mask structures on respective first and second regions of a feature layer. Each of the first and second mask structures includes a dual mask pattern and an etch mask pattern thereon having an etch selectivity relative to the dual mask pattern. The etch mask patterns of the first and second mask structures are etched to partially remove the etch mask pattern from the second mask structure. Spacers are formed on opposing sidewalls of the first and second mask structures. The first mask structure is selectively removed from between the spacers in the first region to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region, and a second mask pattern including the opposing sidewall spacers with the second mask structure therebetween in the second region.

    摘要翻译： 制造集成电路器件的方法包括在特征层的相应的第一和第二区域上形成第一和第二掩模结构。 第一和第二掩模结构中的每一个包括双掩模图案和其上具有相对于双掩模图案的蚀刻选择性的蚀刻掩模图案。 蚀刻第一和第二掩模结构的蚀刻掩模图案以从第二掩模结构部分去除蚀刻掩模图案。 间隔件形成在第一和第二掩模结构的相对侧壁上。 第一掩模结构被选择性地从第一区域中的间隔物之间​​移除，以限定第一掩模图案，其包括在第一区域中具有空隙的相对的侧壁间隔物，以及包括与第二掩模结构相对的侧壁间隔物的第二掩模图案 在第二区域中。

    METHOD OF FORMING PATTERNS FOR SEMICONDUCTOR DEVICE
    6.
    发明申请
    METHOD OF FORMING PATTERNS FOR SEMICONDUCTOR DEVICE 有权
    形成半导体器件的图案的方法

    公开(公告)号：US20140191405A1

    公开(公告)日：2014-07-10

    申请号：US14208456

    申请日：2014-03-13

    申请人： Young-Ho Lee ,  Jae-Hwang Sim ,  Sang-Yong Park ,  Kyung-Lyul Moon

    发明人： Young-Ho Lee ,  Jae-Hwang Sim ,  Sang-Yong Park ,  Kyung-Lyul Moon

    IPC分类号： H01L23/528

    CPC分类号： H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76229 ,  H01L21/76816 ,  H01L21/76838 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/11519 ,  H01L27/11526 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are included in the substrate. Both a blocking pattern covering a portion of the first layer in the first region and a low-density large-width pattern covering a portion of the first layer in the second region are simultaneously formed. A plurality of sacrificial mask patterns are formed on the first layer and the blocking pattern in the first region. A plurality of spacers covering exposed sidewalls of the plurality of sacrificial mask patterns are formed. The plurality of sacrificial mask patterns are removed. The first layer in the first and second regions are simultaneously etched by using the plurality of spacers and the blocking pattern as etch masks in the first region and using the low-density large-width pattern as an etch mask in the second region.

    摘要翻译： 提供一种形成半导体器件的图案的方法，其中精细图案和大幅图案同时并且彼此相邻地形成。 在该方法中，在衬底上形成第一层以覆盖包括在衬底中的第一区域和第二区域。 同时形成覆盖第一区域中的第一层的一部分的阻挡图案和覆盖第二区域中的第一层的一部分的低密度大图案。 在第一层上形成多个牺牲掩模图案，并在第一区域中形成阻挡图案。 形成覆盖多个牺牲掩模图案的暴露侧壁的多个间隔物。 去除多个牺牲掩模图案。 通过使用多个间隔物和阻挡图案作为第一区域中的蚀刻掩模并且在第二区域中使用低密度大宽度图案作为蚀刻掩模，同时蚀刻第一和第二区域中的第一层。

    Method of forming patterns for semiconductor device
    7.
    发明授权
    Method of forming patterns for semiconductor device 有权
    形成半导体器件图案的方法

    公开(公告)号：US08318603B2

    公开(公告)日：2012-11-27

    申请号：US12653588

    申请日：2009-12-16

    申请人： Young-Ho Lee ,  Jae-Hwang Sim ,  Sang-Yong Park ,  Kyung-Lyul Moon

    发明人： Young-Ho Lee ,  Jae-Hwang Sim ,  Sang-Yong Park ,  Kyung-Lyul Moon

    IPC分类号： H01L21/311

    CPC分类号： H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76229 ,  H01L21/76816 ,  H01L21/76838 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/11519 ,  H01L27/11526 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are included in the substrate. Both a blocking pattern covering a portion of the first layer in the first region and a low-density large-width pattern covering a portion of the first layer in the second region are simultaneously formed. A plurality of sacrificial mask patterns are formed on the first layer and the blocking pattern in the first region. A plurality of spacers covering exposed sidewalls of the plurality of sacrificial mask patterns are formed. The plurality of sacrificial mask patterns are removed. The first layer in the first and second regions are simultaneously etched by using the plurality of spacers and the blocking pattern as etch masks in the first region and using the low-density large-width pattern as an etch mask in the second region.

    摘要翻译： 提供一种形成半导体器件的图案的方法，其中精细图案和大幅图案同时并且彼此相邻地形成。 在该方法中，在衬底上形成第一层以覆盖包括在衬底中的第一区域和第二区域。 同时形成覆盖第一区域中的第一层的一部分的阻挡图案和覆盖第二区域中的第一层的一部分的低密度大图案。 在第一层上形成多个牺牲掩模图案，并在第一区域中形成阻挡图案。 形成覆盖多个牺牲掩模图案的暴露侧壁的多个间隔物。 去除多个牺牲掩模图案。 通过使用多个间隔物和阻挡图案作为第一区域中的蚀刻掩模并且在第二区域中使用低密度大宽度图案作为蚀刻掩模，同时蚀刻第一和第二区域中的第一层。

    Methods of forming fine patterns in the fabrication of semiconductor devices
    8.
    发明授权
    Methods of forming fine patterns in the fabrication of semiconductor devices 有权
    在半导体器件的制造中形成精细图案的方法

    公开(公告)号：US08057692B2

    公开(公告)日：2011-11-15

    申请号：US12290420

    申请日：2008-10-30

    申请人： Sang-Yong Park ,  Jae-Hwang Sim ,  Young-Ho Lee ,  Kyung-Lyul Moon ,  Jae-Kwan Park

    发明人： Sang-Yong Park ,  Jae-Hwang Sim ,  Young-Ho Lee ,  Kyung-Lyul Moon ,  Jae-Kwan Park

    IPC分类号： B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00

    CPC分类号： H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/823456 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region. The feature layer is etched using the mask layer patterns as an etch mask in the second region and using the spacers as an etch mask in the first region to provide a feature layer pattern having fine features in the first region and broad features in the second region.

    摘要翻译： 在形成半导体器件的方法中，在衬底上提供特征层，并且在特征层上设置掩模层。 掩模层的一部分在半导体器件的第一区域被去除，其中特征层的精细特征将被定位，掩模层保留在半导体器件的第二区域中，其中特征层的广泛特征将是 位于。 模具掩模图案设置在第一区域中的特征层和第二区域中的掩模层上。 间隔层设置在第一区域和第二区域中的模具掩模图案上。 执行蚀刻工艺以蚀刻间隔层，使得间隔物保留在模具掩模图案的图案特征的侧壁处，并且蚀刻第二区域中的掩模层以在第二区域中提供掩模层图案。 使用掩模层图案作为第二区域中的蚀刻掩模蚀刻特征层，并且在第一区域中使用间隔物作为蚀刻掩模来提供在第一区域中具有精细特征的特征层图案，并且在第二区域中具有广泛特征 。

    DUAL-COOLED NUCLEAR FUEL ROD HAVING ANNULAR PLUGS AND METHOD OF MANUFACTURING THE SAME
    9.
    发明申请
    DUAL-COOLED NUCLEAR FUEL ROD HAVING ANNULAR PLUGS AND METHOD OF MANUFACTURING THE SAME 有权
    具有环形管的双冷却核燃料棒及其制造方法

    公开(公告)号：US20100266094A1

    公开(公告)日：2010-10-21

    申请号：US12559059

    申请日：2009-09-14

    申请人： Hyung-Kyu Kim ,  Jong-Hun Kim ,  Dae-Ho Kim ,  Kun-Woo Song ,  Kyung-Ho Yoon ,  Young-Ho Lee ,  Jae-Yong Kim ,  Kang-Hee Lee

    发明人： Hyung-Kyu Kim ,  Jong-Hun Kim ,  Dae-Ho Kim ,  Kun-Woo Song ,  Kyung-Ho Yoon ,  Young-Ho Lee ,  Jae-Yong Kim ,  Kang-Hee Lee

    IPC分类号： G21C3/16 ,  C21D1/40

    CPC分类号： G21C3/02 ,  G21C3/10 ,  G21C21/02 ,  Y02E30/40

    摘要： A dual-cooled nuclear fuel rod and a method of manufacturing the same are provided. The nuclear fuel rod includes an outer cladding tube having a circular cross section, an inner cladding tube having an outer diameter smaller than an inner diameter of the outer cladding tube, and a length longer than the outer cladding tube, and located in parallel in the outer cladding tube, a pellet charged in a space between the outer and inner cladding tubes and generating energy by nuclear fission, and first and second end plugs coupling opposite ends of the outer cladding tube to stepped outer joints formed on outer circumferences of first ends thereof and coupling opposite ends of the inner cladding tube to stepped inner joints formed on inner circumferences of the first ends thereof.

    摘要翻译： 提供了双冷核燃料棒及其制造方法。 核燃料棒包括具有圆形横截面的外包层管，外包层的外径小于外包层管的内径，长度比外包层管长，并且平行于 外包层管，填充在外包层管和内包壳管之间的空间中并通过核裂变产生能量的颗粒，以及将外包层管的相对端连接到形成在其第一端的外周上的阶梯式外接头的第一和第二端塞 并且将内包层管的相对端连接到形成在其第一端的内周上的阶梯式内接头。

    Method of forming patterns for semiconductor device
    10.
    发明申请
    Method of forming patterns for semiconductor device 有权
    形成半导体器件图案的方法

    公开(公告)号：US20100221919A1

    公开(公告)日：2010-09-02

    申请号：US12653588

    申请日：2009-12-16

    申请人： Young-Ho Lee ,  Jae-Hwang Sim ,  Sang-Yong Park ,  Kyung-Lyul Moon

    发明人： Young-Ho Lee ,  Jae-Hwang Sim ,  Sang-Yong Park ,  Kyung-Lyul Moon

    IPC分类号： H01L21/302

    CPC分类号： H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76229 ,  H01L21/76816 ,  H01L21/76838 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/11519 ,  H01L27/11526 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are included in the substrate. Both a blocking pattern covering a portion of the first layer in the first region and a low-density large-width pattern covering a portion of the first layer in the second region are simultaneously formed. A plurality of sacrificial mask patterns are formed on the first layer and the blocking pattern in the first region. A plurality of spacers covering exposed sidewalls of the plurality of sacrificial mask patterns are formed. The plurality of sacrificial mask patterns are removed. The first layer in the first and second regions are simultaneously etched by using the plurality of spacers and the blocking pattern as etch masks in the first region and using the low-density large-width pattern as an etch mask in the second region.

    摘要翻译： 提供一种形成半导体器件的图案的方法，其中精细图案和大幅图案同时并且彼此相邻地形成。 在该方法中，在衬底上形成第一层以覆盖包括在衬底中的第一区域和第二区域。 同时形成覆盖第一区域中的第一层的一部分的阻挡图案和覆盖第二区域中的第一层的一部分的低密度大图案。 在第一层上形成多个牺牲掩模图案，并在第一区域中形成阻挡图案。 形成覆盖多个牺牲掩模图案的暴露侧壁的多个间隔物。 去除多个牺牲掩模图案。 通过使用多个间隔物和阻挡图案作为第一区域中的蚀刻掩模并且在第二区域中使用低密度大宽度图案作为蚀刻掩模，同时蚀刻第一和第二区域中的第一层。