公开(公告)号：US20150270007A1

公开(公告)日：2015-09-24

申请号：US14219315

申请日：2014-03-19

Applicant: Apple Inc.

Inventor： Naftali Sommer ,  Avraham Poza Meir ,  Yoav Kasorla ,  Eyal Gurgi

IPC: G11C16/34 ,  G11C16/28

CPC classification number: G11C16/3404 ,  G11C7/02 ,  G11C7/04

Abstract: A method includes storing data values in a group of memory cells that share a common isolating layer, by producing quantities of electrical charge representative of the data values at respective regions of the common isolating layer that are associated with the memory cells. A function, which relates a drift of the electrical charge in a given memory cell in the group to the data values stored in one or more other memory cells in the group, is estimated. The drift is compensated for using the estimated function.

Abstract translation: 一种方法包括通过产生表示与存储器单元相关联的公共隔离层的各个区域处的数据值的电荷量来将数据值存储在共享公共隔离层的一组存储器单元中。 估计将组中的给定存储单元中的电荷的漂移与存储在组中的一个或多个其他存储单元中的数据值相关联的功能。 使用估计功能补偿漂移。

公开(公告)号：US09136015B2

公开(公告)日：2015-09-15

申请号：US13908041

申请日：2013-06-03

Applicant: Apple Inc.

Inventor： Micha Anholt ,  Eyal Gurgi ,  Barak Baum ,  Moshe Neerman ,  Moti Teitel

IPC: G11C29/00 ,  G11C29/02 ,  G06F11/10 ,  G11C29/42 ,  G11C11/56 ,  G11C16/00

CPC classification number: G11C29/021 ,  G06F11/1072 ,  G11C11/56 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/00 ,  G11C29/028 ,  G11C29/42

Abstract: A method, in a memory including multiple analog memory cells, includes segmenting a group of the memory cells into a common section and at least first and second dedicated sections. Each dedicated section corresponds to a read threshold that is used for reading a data page to be stored in the group. Data to be stored in the group is jointly balanced over a union of the common section and the first dedicated section, and over the union of the common section and the second dedicated section, to create a balanced page such that for each respective read threshold an equal number of memory cells will be programmed to assume programming levels that are separated by the read threshold. The balanced page is stored to the common and dedicated sections, and the read thresholds are adjusted based on detecting imbalance between data values in readout results of the balanced page.

Abstract translation: 一种在包括多个模拟存储器单元的存储器中的方法包括将一组存储器单元分成公共部分和至少第一和第二专用部分。 每个专用部分对应于用于读取要存储在组中的数据页的读取阈值。 要存储在组中的数据通过公共部分和第一专用部分的并集，并且在公共部分和第二专用部分的联合之间共同平衡，以创建平衡页面，使得对于每个相应的读取阈值 相同数量的存储器单元将被编程为假设由读取阈值分开的编程电平。 平衡页面存储到公共和专用部分，并且基于检测平衡页面的读出结果中的数据值之间的不平衡来调整读取阈值。

公开(公告)号：US20150199999A1

公开(公告)日：2015-07-16

申请号：US14468661

申请日：2014-08-26

Applicant: Apple Inc.

Inventor： Naftali Sommer ,  Stas Mouler ,  Eyal Gurgi ,  Yoav Kasorla ,  Liran Erez

IPC: G11C5/14

CPC classification number: G11C5/14 ,  G11C5/145 ,  G11C5/147 ,  G11C16/10 ,  G11C16/12 ,  G11C16/30 ,  G11C16/32

Abstract: A method includes, in a storage system that includes multiple memory devices, holding a definition of a given type of storage command. Multiple storage commands of the given type are executed in the memory devices, such that an actual current consumption of each storage command deviates from a nominal current waveform defined for the given type by no more than a predefined deviation, and such that each storage command is preceded by a random delay.

Abstract translation: 一种方法包括在包括多个存储设备的存储系统中，保持给定类型的存储命令的定义。 给定类型的多个存储命令在存储器件中被执行，使得每个存储命令的实际电流消耗偏离为给定类型定义的额定电流波形不超过预定义的偏差，并且使得每个存储命令是 之前是随机延迟。

公开(公告)号：US20150012686A1

公开(公告)日：2015-01-08

申请号：US13935746

申请日：2013-07-05

Applicant: Apple Inc.

Inventor： Avraham Poza Meir ,  Eyal Gurgi ,  Shai Ojalvo ,  Yoav Kasorla ,  Naftali Sommer

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7211

Abstract: A method for data storage in a memory that includes multiple analog memory cells, includes defining, based on a characteristic of the memory cells, an uneven wear leveling scheme that programs and erases at least first and second subsets of the memory cells with respective different first and second Programming and Erasure (P/E) rates. Data is stored in the memory in accordance with the uneven wear leveling scheme.

Abstract translation: 一种用于在包括多个模拟存储器单元的存储器中的数据存储的方法，包括基于所述存储器单元的特性定义不均匀磨损平衡方案，所述不均匀磨损均衡方案以相应不同的第一方式来编程和擦除所述存储器单元的至少第一和第二子集 和第二个编程和擦除（P / E）率。 根据不均匀的磨损均衡方案将数据存储在存储器中。

公开(公告)号：US20140355341A1

公开(公告)日：2014-12-04

申请号：US14341991

申请日：2014-07-28

Applicant: Apple Inc.

Inventor： Barak Baum ,  Eyal Gurgi

IPC: G11C16/26

CPC classification number: G11C16/26 ,  G11C7/065 ,  G11C11/5642 ,  G11C16/3404 ,  G11C29/021 ,  G11C29/028

Abstract: A method includes dividing a group of analog memory cells into multiple subsets. The memory cells in the group are sensed simultaneously by performing a single sense operation, while applying to the subsets of the memory cells respective different sets of read thresholds, so as to produce respective readout results. An optimal set of the read thresholds is estimated by processing the multiple readout results obtained from the respective subsets using the different sets of the read thresholds.

Abstract translation: 一种方法包括将一组模拟存储器单元划分成多个子集。 通过执行单次感测操作同时对组中的存储器单元同时应用各存储器单元的子集各自不同的读取阈值集合，从而产生相应的读出结果。 通过使用不同的读取阈值集处理从各个子集获得的多个读出结果来估计读取阈值的最佳集合。

公开(公告)号：US20140340951A1

公开(公告)日：2014-11-20

申请号：US14450903

申请日：2014-08-04

Applicant: Apple Inc.

Inventor： Yael Shur ,  Yoav Kasorla ,  Eyal Gurgi

IPC: G11C27/00

CPC classification number: G11C27/00 ,  G11C7/00 ,  G11C13/0002 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C27/005

Abstract: A method includes, in an array of analog memory cells that are arranged in rows associated with respective word lines, reading a first group of the memory cells in a selected word line, including one or more memory cells that store a status of at least one word line in the array other than the selected word line. A readout configuration for a second group of the memory cells is set responsively to the read status. The second group of the memory cells is read using the readout configuration.

公开(公告)号：US20140313832A1

公开(公告)日：2014-10-23

申请号：US13865351

申请日：2013-04-18

Applicant: APPLE INC.

Inventor： Avraham Poza Meir ,  Eyal Gurgi ,  Naftali Sommer ,  Yoav Kasorla

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/3454 ,  G11C16/3459

Abstract: A method includes storing data in a memory, which includes multiple strings of analog memory cells arranged in a three-dimensional (3-D) configuration having a first dimension associated with bit lines, a second dimension associated with word lines and a third dimension associated with sections, such that each string is associated with a respective bit line and a respective section and includes multiple memory cells that are connected to the respective word lines. For a group of the strings, respective values of a property of the strings in the group are evaluated. Source-side voltages are calculated for the respective strings in the group, depending on the respective values of the property, and respective source-sides of the strings in the group are biased with the corresponding source-side voltages. A memory operation is performed on the strings in the group while the strings are biased with the respective source-side voltages.

Abstract translation: 一种方法包括将数据存储在存储器中，其包括以具有与位线相关联的第一维度的三维（3-D）配置布置的多个模拟存储器单元串，与字线相关联的第二维度和与第三维度相关联的第三维度 具有部分，使得每个字符串与相应的位线和相应的部分相关联，并且包括连接到各个字线的多个存储器单元。 对于一组字符串，对组中字符串的属性的各个值进行评估。 根据属性的各个值，针对组中的各个串来计算源侧电压，并且组中的串的各个源侧被相应的源极侧电压偏置。 当串被相应的源侧电压偏置时，对组中的串执行存储器操作。

公开(公告)号：US08824214B2

公开(公告)日：2014-09-02

申请号：US13709267

申请日：2012-12-10

Applicant: Apple Inc.

Inventor： Yael Shur ,  Yoav Kasorla ,  Eyal Gurgi

IPC: G11C7/22 ,  G11C7/00

CPC classification number: G11C7/00 ,  G11C13/0002 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C27/005

Abstract: A method includes selecting a word line for programming in an array of analog memory cells that are arranged in rows associated with respective word lines and columns associated with respective bit lines. Word-line voltages, which program the memory cells in the selected word line, are applied to the respective word lines. Bit-line voltages, which cause one or more additional memory cells outside the selected word line to be programmed as a result of programming the selected word line, are applied to the respective bit lines. Using the applied word-line and bit-line voltages, data is stored in the memory cells in the selected word line and the additional memory cells are simultaneously programmed.

Abstract translation: 一种方法包括选择用于在与相应字线相关联的行中排列的模拟存储器单元阵列中编程的字线，所述行与相应位线相关联。 将所选字线中的存储单元编程的字线电压施加到相应的字线。 将所选择的字线外部的一个或多个附加存储单元作为所选字线编程的结果编程的位线电压被施加到相应的位线。 使用所应用的字线和位线电压，将数据存储在所选字线中的存储单元中，并且附加存储单元被同时编程。

公开(公告)号：US20140052940A1

公开(公告)日：2014-02-20

申请号：US13709656

申请日：2012-12-10

Applicant: APPLE INC.

Inventor： Eyal Gurgi ,  Yael Shur ,  Yoav Kasorla

IPC: G06F12/00

CPC classification number: G06F12/00 ,  G06F12/02

Abstract: A method for data storage includes providing at least first and second readout schemes for reading storage values from a group of analog memory cells that are connected to respective bit lines. The first readout scheme reads the storage values using a first bit line charging configuration having a first sense time, and the second readout scheme reads the storage values using a second bit line charging configuration having a second sense time, shorter than the first sense time. A condition is evaluated with respect to a read operation that is to be performed over a group of the memory cells. One of the first and second readout schemes is selected responsively to the evaluated condition. The storage values are read from the group of the memory cells using the selected readout scheme.

Abstract translation: 一种用于数据存储的方法包括提供至少第一和第二读出方案，用于从连接到各个位线的一组模拟存储器单元读取存储值。 第一读出方案使用具有第一感测时间的第一位线充电配置读取存储值，并且第二读出方案使用比第一感测时间短的具有第二感测时间的第二位线充电配置来读取存储值。 针对要在一组存储器单元上执行的读取操作来评估条件。 响应于评估条件选择第一和第二读出方案中的一个。 使用所选择的读出方案从存储器单元的组中读取存储值。

公开(公告)号：US10936455B2

公开(公告)日：2021-03-02

申请号：US16271907

申请日：2019-02-11

Applicant: Apple Inc.

Inventor： Eli Yazovitsky ,  Eyal Gurgi ,  Michael Tsohar

IPC: G06F11/20

Abstract: A controller includes an interface and storage circuitry. The interface communicates with a memory that includes memory cells that store data in multiple programming levels, and that are organized in Word Lines (WLs). Each WL connects to one or more cell-groups of the memory cells. The memory cells in some cell-groups suffer from an impairment that has a different severity for reading data units of different bit-significance values. The storage circuitry assigns multiple parity groups to data units stored in cell-groups belonging to consecutive WLs, so that a same parity group is assigned to data units of different bit-significance values in neighboring groups of Nwl consecutive WLs. Upon detecting a failure to access a data unit of a given parity group, due to the impairment, the storage circuitry recovers the data unit using other data units assigned to the given parity group, and that are stored in other cell-groups.