公开(公告)号：US20240103754A1

公开(公告)日：2024-03-28

申请号：US17936345

申请日：2022-09-28

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Gia Tung Phan ,  Ashish Jain ,  Chintan S. Patel ,  Benjamin Tsien ,  Jun Lei ,  Shang Yang ,  Oswin Hall

IPC: G06F3/06

CPC classification number: G06F3/0653 ,  G06F3/0604 ,  G06F3/0634 ,  G06F3/0679

Abstract: Systems, apparatuses, and methods for prefetching data by a display controller. From time to time, a performance-state change of a memory are performed. During such changes, a memory clock frequency is changed for a memory subsystem storing frame buffer(s) used to drive pixels to a display device. During the performance-state change, memory accesses may be temporarily blocked. In order to reduce visual artifacts that may occur while the memory accesses are blocked, a memory subsystem includes a control circuit configured to enable a caching mode which caches display data provided to the display controller. Subsequent requests for display data from the display controller are then serviced using the cached data instead of accessing memory.

公开(公告)号：US11940858B2

公开(公告)日：2024-03-26

申请号：US17973061

申请日：2022-10-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien ,  Amit P. Apte

IPC: G06F1/3228 ,  G06F1/3234 ,  G06F1/3296 ,  G06F12/0831 ,  G06F13/26

CPC classification number: G06F1/3228 ,  G06F1/3275 ,  G06F1/3296 ,  G06F12/0833 ,  G06F13/26 ,  Y02D10/00

Abstract: A data fabric routes requests between the plurality of requestors and the plurality of responders. The data fabric includes a crossbar router, a coherent slave controller coupled to the crossbar router, and a probe filter coupled to the coherent slave controller and tracking the state of cached lines of memory. Power state control circuitry operates, responsive to detecting any of a plurality of designated conditions, to cause the probe filter to enter a retention low power state in which a clock signal to the probe filter is gated while power is maintained to the probe filter. Entering the retention low power state is performed when all in-process probe filter lookups are complete.

公开(公告)号：US20240004815A1

公开(公告)日：2024-01-04

申请号：US17853842

申请日：2022-06-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael J. Tresidder ,  Benjamin Tsien

IPC: G06F13/364 ,  G06F9/48

CPC classification number: G06F13/364 ,  G06F9/4893

Abstract: Systems and methods are disclosed for scheduling a data link training by a controller. The system and method include receiving an indication that a physical layer of a data link is not transferring data and initiating a training process of the physical layer of the data link in response to the indication that the physical layer of the data link is not transferring data. In one aspect, the indication that the physical layer of a data link is not transferring data is an indication that the physical layer of the data link is in a low power state. In another aspect, the indication that the physical layer of a data link is not transferring data is an indication that a data transfer has been completed.

公开(公告)号：US20230315188A1

公开(公告)日：2023-10-05

申请号：US17710521

申请日：2022-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander J. Branover ,  Thomas J. Gibney ,  Mihir Shaileshbhai Doctor ,  Indrani Paul ,  Benjamin Tsien ,  Stephen V. Kosonocky ,  John P. Petry ,  Christopher T. Weaver

IPC: G06F1/3234

CPC classification number: G06F1/3234

Abstract: Methods and systems are disclosed for transitioning, by a hardware-based controller, a system on a chip (SoC) into different power states. Techniques disclosed include tracking, by the controller, metrics associated with the SoC and transitioning, by the controller, the SoC from a first power state to a second power state based on the tracked metrics. Were the total amount of power that is used by at least a portion of the transition between the first power state to the second power state and a time spent in the second power state is less than the total amount of power that would have been used by remaining in the first power state.

公开(公告)号：US11734151B2

公开(公告)日：2023-08-22

申请号：US17357200

申请日：2021-06-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien ,  Pravesh Gupta

IPC: G06F11/34

CPC classification number: G06F11/349 ,  G06F11/3409

Abstract: An integrated circuit (IC) includes a first circuit including a timer for receiving an adjustable clock signal. Responsive to leaving the non-operational power state to enter a power state in which the adjustable clock has a lower frequency than the reference clock, the first circuit adjusts the frequency of the adjustable clock to a frequency higher than the lower frequency, and then receives an elapsed time associated with the non-operational power state and starts the timer using an adjusted timer value.

公开(公告)号：US11703932B2

公开(公告)日：2023-07-18

申请号：US17357047

申请日：2021-06-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien ,  Amit P. Apte

IPC: G06F1/32 ,  G06F1/3234

CPC classification number: G06F1/3234

Abstract: A data fabric routes requests between the plurality of requestors. A probe filter tracks the state of cached lines of memory at a probe filter coupled to the data fabric. Responsive to the data fabric leaving a non-operational power state while all requestors that are probe filter clients are in a non-operational power state, the power management controller delays a probe filter initialization state in which data regarding cached lines is initialized following the non-operational power state.

公开(公告)号：US20230185623A1

公开(公告)日：2023-06-15

申请号：US18164315

申请日：2023-02-03

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander J. Branover ,  Benjamin Tsien ,  Elliot H. Mednick

IPC: G06F9/50 ,  G06F11/30

CPC classification number: G06F9/5044 ,  G06F9/5094 ,  G06F11/3062 ,  G06F11/3024 ,  G06F2209/508 ,  G06F2209/501

Abstract: A method, system, and apparatus determines whether a task should be relocated from a first processor to a second processor by comparing performance metrics to associated thresholds or by using other indications. The task is relocated from the first processor to the second processor and executed on the second processor based on the com paring.

公开(公告)号：US20230095622A1

公开(公告)日：2023-03-30

申请号：US17485194

申请日：2021-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander J. Branover ,  Indrani Paul ,  Benjamin Tsien ,  Christopher T. Weaver ,  John P. Petry ,  Mihir Shaileshbhai Doctor ,  Thomas J. Gibney

IPC: G06F1/26 ,  G06F13/40

Abstract: A method and apparatus for isolating and restoring general-purpose input/output (GPIO) pads in a computer system includes identifying GPIO pads associated with the region responsive to an entry into a power-down state of a region of a circuit. The GPIO pads are isolated from one or more external circuits. Upon exit from the power-down state, each associated GPIO pad is restored to a current value.

公开(公告)号：US20230031295A1

公开(公告)日：2023-02-02

申请号：US17390475

申请日：2021-07-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Thomas J. Gibney ,  Alexander J. Branover ,  Mihir Shaileshbhai Doctor ,  Xiaojie He ,  Indrani Paul ,  Benjamin Tsien ,  John P. Petry ,  Pitchaiah Katari

IPC: G06F1/324 ,  G06F1/3237 ,  G06F1/3218 ,  G06F1/08

Abstract: A disclosed technique includes triggering entry into a clock bypass mode, in which a bypass clock generator provides clock signals to functional elements and a primary clock generator does not provide clock signals to functional elements; and triggering exit from the clock bypass mode, in which the bypass clock generator does not provide clock signals to the functional elements and the primary clock generator does provide clock signals to the functional elements.

公开(公告)号：US20220091657A1

公开(公告)日：2022-03-24

申请号：US17031739

申请日：2020-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien

IPC: G06F1/3228 ,  G06F9/48

Abstract: Systems, apparatuses, and methods for efficient power management of a multi-node computing system are disclosed. A computing system includes multiple nodes that receive tasks to process. The nodes include a processor, local memory, a power controller, and multiple link interfaces for transferring messages with other nodes across links. Using a distributed approach for power management, negotiation for powering down components of the computing system occurs without performing a centralized system-wide power down. Each node is able to power down its links, its processor and other components regardless of whether other components of the computing system are still active or powered up. A link interface initiates power down of a link with delay or without delay based on a prediction of whether a link idle condition leads to the link interface remaining idle for at least a target idle threshold period of time.