公开(公告)号：US12181944B2

公开(公告)日：2024-12-31

申请号：US17562854

申请日：2021-12-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander J. Branover ,  Thomas J. Gibney ,  Stephen V. Kosonocky ,  Mihir Shaileshbhai Doctor ,  John P. Petry ,  Indrani Paul ,  Benjamin Tsien ,  Christopher T. Weaver

IPC: G06F1/3206

Abstract: A method and apparatus for managing power states in a computer system includes, responsive to an event received by a processor, powering up a first circuitry. Responsive to the event not being serviceable by the first circuitry, powering up at least a second circuitry of the computer system to service the event.

公开(公告)号：US12130692B2

公开(公告)日：2024-10-29

申请号：US17993562

申请日：2022-11-23

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Karthik Rao ,  Indrani Paul ,  Donny Yi ,  Oleksandr Khodorkovsky ,  Leonardo De Paula Rosa Piga ,  Wonje Choi ,  Dana G. Lewis ,  Sriram Sambamurthy

IPC: G06F1/32 ,  G06F1/3287

CPC classification number: G06F1/3287

Abstract: An apparatus includes a processor, a sleep state duration prediction module, and a system management unit. The sleep state duration prediction module is configured to predict a sleep state duration for component of the processing device. The system management unit is to transition the component into a sleep state selected from a plurality of sleep states based on a comparison of the predicted sleep state duration to at least one duration threshold. Each sleep state of the plurality of sleep states is a lower power state than a previous sleep state of the plurality of sleep states.

公开(公告)号：US12130690B2

公开(公告)日：2024-10-29

申请号：US18316865

申请日：2023-05-12

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Alexander J. Branover ,  Christopher T. Weaver ,  Benjamin Tsien ,  Indrani Paul ,  Mihir Shaileshbhai Doctor ,  Thomas J. Gibney ,  John P. Petry ,  Dennis Au ,  Oswin Hall

IPC: G06F1/32 ,  G06F1/3209 ,  G06F1/3234

CPC classification number: G06F1/3265 ,  G06F1/3209 ,  G06F1/3275

Abstract: A method and system for operating in a single display mode operation and a dual pipe mode of operation is disclosed. The method and system includes operating in a dual pipe mode of operation in which each display pipe transmits data from a respective buffer to an associated display. The method and system further includes operating in a single display mode of operation in which one display pipe transmits data from a plurality of buffers to an associated display.

公开(公告)号：US12072754B2

公开(公告)日：2024-08-27

申请号：US17485199

申请日：2021-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander J. Branover ,  Christopher T. Weaver ,  Indrani Paul ,  Benjamin Tsien ,  Mihir Shaileshbhai Doctor ,  Stephen V. Kosonocky ,  John P. Petry ,  Thomas J. Gibney

IPC: G06F1/00 ,  G06F1/3296

CPC classification number: G06F1/3296

Abstract: A method and apparatus for managing a controller includes indicating, by a processor of a first device, to the controller of a second device to enter a second power state from a first power state. The controller of the second device responds to the processor of the first device with a confirmation. The processor of the first device transmits a signal to the controller of the second device to enter the second power state. Upon receiving a wake event, the controller of the second device exits the second device from the second power state to the first power state.

公开(公告)号：US11886878B2

公开(公告)日：2024-01-30

申请号：US16712891

申请日：2019-12-12

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Sukesh Shenoy ,  Adam N. C. Clark ,  Indrani Paul

IPC: G06F1/00 ,  G06F9/30 ,  G06F9/48 ,  G06F1/3203 ,  G06F9/38

CPC classification number: G06F9/30083 ,  G06F1/3203 ,  G06F9/3877 ,  G06F9/4843 ,  G06F2009/3883

Abstract: An integrated coprocessor such as an accelerated processing unit (APU) generates commands for execution on a discrete coprocessor such as a discrete graphics processing unit (dGPU). Power distribution circuitry selectively provides power to the APU and the dGPU based on characteristics of workloads executing on the APU and the dGPU and based on a platform power limit that is shared by the APU and the dGPU. In some cases, the power distribution circuitry determines a first power provided to the APU and a second power provided to the dGPU. The power distribution circuitry increases the second power provided to the dGPU in response to a sum of the first and second powers being less than the platform power limit. In some cases, the power distribution circuitry modifies the power provided to the APU, the dGPU, or both in response to changes in temperatures measured by a set of sensors.

公开(公告)号：US20240004453A1

公开(公告)日：2024-01-04

申请号：US17854858

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Ashwini Chandrashekhara Holla ,  Alexander S. Duenas ,  Xinzhe Li ,  Indrani Paul ,  Karthik Rao

IPC: G06F1/324

CPC classification number: G06F1/324

Abstract: Methods and systems are disclosed for managing the power consumed by cores of a system on chip (SoC). Techniques disclosed include obtaining application information that is indicative of an application being executed on the cores, detecting a workload associated with the application, and limiting one or more operating frequencies of the cores responsive to the detection of the workload. Techniques disclosed also include profiling the detected workload and limiting the one or more operating frequencies of the cores based on the profiling.

公开(公告)号：US20240004444A1

公开(公告)日：2024-01-04

申请号：US17855054

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Karthik Rao ,  Indrani Paul ,  Dana Glenn Lewis ,  Brett Danier Anil Ramautarsingh ,  Jeffrey Ka-Chun Lui ,  Prasanthy Loganaathan ,  Jun Huang ,  Ho Hin Lau ,  Zhidong Xu

IPC: G06F1/26

CPC classification number: G06F1/26

Abstract: Methods and systems are disclosed for managing performance states of a data fabric of a system on chip (SoC). Techniques disclosed include determining a performance state of the data fabric based on data fabric bandwidth utilizations of respective components of the SoC. A metric, characteristic of a workload centric to cores of the SoC, is derived from hardware counters, and, based on the metric, it is determined whether to alter the performance state.

公开(公告)号：US20230418664A1

公开(公告)日：2023-12-28

申请号：US17846593

申请日：2022-06-22

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Donny Yi ,  Indrani Paul ,  Ashwini Chandrashekhara Holla

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/50 ,  G06F9/30

CPC classification number: G06F9/4881 ,  G06F9/3836 ,  G06F9/5038 ,  G06F9/5044 ,  G06F9/30079

Abstract: An apparatus and method for efficiently scheduling tasks in a dynamic manner to multiple cores that support a heterogeneous computing architecture. A computing system includes multiple cores with at least two cores being capable of executing instructions of a same instruction set architecture (ISA), and therefore, are architecturally compatible. In an implementation, each of the at least two cores is a general-purpose central processing unit (CPU) core capable of executing instructions of a same ISA. However, the throughput and the power consumption greatly differ between the at least two cores based on their hardware designs. An operating system scheduler assigns a thread to a first core, and the first core measures thread dynamic behavior of the thread over a time interval. Based on the thread dynamic behavior, the scheduler reassigns the thread to a second core different from the first core.

公开(公告)号：US20230350480A1

公开(公告)日：2023-11-02

申请号：US18213596

申请日：2023-06-23

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Indrani Paul ,  Sriram Sambamurthy ,  Larry David Hewitt ,  Kevin M. Lepak ,  Samuel D. Naffziger ,  Adam Neil Calder Clark ,  Aaron Joseph Grenat ,  Steven Frederick Liepe ,  Sandhya Shyamasundar ,  Wonje Choi ,  Dana Glenn Lewis ,  Leonardo de Paula Rosa Piga

IPC: G06F1/3225 ,  G06F1/3234

CPC classification number: G06F1/3225 ,  G06F1/3275 ,  G06F1/3203

Abstract: Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or budget.

公开(公告)号：US11703937B2

公开(公告)日：2023-07-18

申请号：US17483698

申请日：2021-09-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Mihir Shaileshbhai Doctor ,  Alexander J. Branover ,  Benjamin Tsien ,  Indrani Paul ,  Christopher T. Weaver ,  Thomas J. Gibney ,  Stephen V. Kosonocky ,  John P. Petry

IPC: G06F1/32 ,  G06F1/3287 ,  G06F1/3296 ,  G06F1/3234

CPC classification number: G06F1/3287 ,  G06F1/3265 ,  G06F1/3278 ,  G06F1/3296

Abstract: Devices and methods for linear addressing are provided. A device is provided which comprises a plurality of components having assigned registers used to store data to execute a program and a power management controller, in communication with the components. The power management controller is configured to send one of a request to remove power to the components and a request to reduce power to the components when it is determined that the components are idle, execute a first process of one of removing power and reducing power to the components and entering a reduced power state when an acknowledgement of the request is received and execute a second process of restoring power to the components when one or more of the components are indicated to be active.