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    MEMORY DEVICES HAVING SOURCE LINES DIRECTLY COUPLED TO BODY REGIONS AND METHODS
    83.
    发明申请
    MEMORY DEVICES HAVING SOURCE LINES DIRECTLY COUPLED TO BODY REGIONS AND METHODS 有权
    具有直接连接到区域和方法的源线的存储器件

    公开(公告)号：US20120188825A1

    公开(公告)日：2012-07-26

    申请号：US13011223

    申请日：2011-01-21

    申请人： Akira Goda

    发明人： Akira Goda

    IPC分类号： G11C16/04 ,  H01L29/78

    CPC分类号： G11C16/14 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/11556

    摘要： Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body region to a source line. Configurations and methods shown should provide a reliable bias to a body region for memory operations such as erasing.

    摘要翻译： 显示了存储器件，存储器单元串和操作存储器件的方法。 所描述的配置包括将细长体区直接耦合到源线。 显示的配置和方法应为存储器操作（如擦除）提供可靠的身体区域偏置。

    SENSE OPERATION IN A MEMORY DEVICE
    84.
    发明申请
    SENSE OPERATION IN A MEMORY DEVICE 有权
    在存储器件中的感测操作

    公开(公告)号：US20120182797A1

    公开(公告)日：2012-07-19

    申请号：US13009540

    申请日：2011-01-19

    申请人： Yijie Zhao ,  Akira Goda ,  Mark A. Helm

    发明人： Yijie Zhao ,  Akira Goda ,  Mark A. Helm

    IPC分类号： G11C16/04

    CPC分类号： G11C16/04 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3422 ,  G11C2211/5641

    摘要： Methods for sensing and memory devices are disclosed. One such method for sensing determines a threshold voltage of an n-bit memory cell that is adjacent to an m-bit memory cell to be sensed. A control gate of the m-bit memory cell to be sensed is biased with a sense voltage adjusted responsive to the determined threshold voltage of the n-bit memory cell.

    摘要翻译： 公开了用于感测和存储器件的方法。 一种用于感测的方法确定与要感测的m位存储器单元相邻的n位存储器单元的阈值电压。 要感测的m位存储器单元的控制栅极利用响应于所确定的n位存储单元的阈值电压而调整的感测电压进行偏置。

    Reducing effects of erase disturb in a memory device
    85.
    发明授权
    Reducing effects of erase disturb in a memory device 有权
    减少存储器件中擦除干扰的影响

    公开(公告)号：US08203876B2

    公开(公告)日：2012-06-19

    申请号：US12628522

    申请日：2009-12-01

    申请人： Akira Goda ,  Alessandro Torsi ,  Carlo Musilli ,  Mark A. Helm ,  Doyle Rivers

    发明人： Akira Goda ,  Alessandro Torsi ,  Carlo Musilli ,  Mark A. Helm ,  Doyle Rivers

    IPC分类号： G11C16/04

    CPC分类号： G11C16/3418 ,  G11C16/0483 ,  G11C16/14

    摘要： Methods for programming and memory devices are disclosed. One such method for programming includes initially biasing a subset of a plurality of control gates of a string of memory cells with a negative voltage, wherein the subset is less than all of the plurality of control gates of the string. The control gate of a selected memory cell is subsequently biased with a programming voltage during a programming phase.

    摘要翻译： 公开了用于编程和存储器件的方法。 一种用于编程的方法包括：初始地利用负电压偏置存储器单元串的多个控制栅极的子集，其中该子集小于该串的多个控制栅极的全部。 在编程阶段期间，所选择的存储单元的控制栅随后用编程电压进行偏置。

    MEMORY ARRAYS WHERE A DISTANCE BETWEEN ADJACENT MEMORY CELLS AT ONE END OF A SUBSTANTIALLY VERTICAL PORTION IS GREATER THAN A DISTANCE BETWEEN ADJACENT MEMORY CELLS AT AN OPPOSING END OF THE SUBSTANTIALLY VERTICAL PORTION AND FORMATION THEREOF
    87.
    发明申请
    MEMORY ARRAYS WHERE A DISTANCE BETWEEN ADJACENT MEMORY CELLS AT ONE END OF A SUBSTANTIALLY VERTICAL PORTION IS GREATER THAN A DISTANCE BETWEEN ADJACENT MEMORY CELLS AT AN OPPOSING END OF THE SUBSTANTIALLY VERTICAL PORTION AND FORMATION THEREOF 有权
    在主要垂直部分的一端的相邻记忆细胞之间的距离在主要垂直部分的相对端和其形成之间的相邻存储细胞之间的距离更大的存储器阵列

    公开(公告)号：US20120091521A1

    公开(公告)日：2012-04-19

    申请号：US12903264

    申请日：2010-10-13

    申请人： Akira Goda

    发明人： Akira Goda

    IPC分类号： H01L29/68 ,  H01L21/336

    CPC分类号： H01L29/66666 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

    摘要： Memory arrays and their formation are disclosed. One such memory array has a string of series-coupled memory cells with a substantially vertical portion. A distance between adjacent memory cells at one end of the substantially vertical portion is greater than a distance between adjacent memory cells at an opposing end of the substantially vertical portion. For other embodiments, thicknesses of respective control gates of the memory cells and/or thicknesses of the dielectrics between successively adjacent control gates may increase as the distances of the respective control gates/dielectrics from the opposing end of the substantially vertical portion increase.

    摘要翻译： 公开了存储器阵列及其形成。 一个这样的存储器阵列具有串联耦合的存储器单元串，其具有基本垂直的部分。 在基本垂直部分的一端处的相邻存储单元之间的距离大于在基本垂直部分的相对端处的相邻存储单元之间的距离。 对于其他实施例，存储单元的相应控制栅极的厚度和/或连续相邻的控制栅极之间的电介质的厚度可以随着各个控制栅极/电介质与基本垂直部分的相对端的距离增加而增加。

    Memory cell operation
    88.
    发明授权
    Memory cell operation 有权
    存储单元操作

    公开(公告)号：US08116137B2

    公开(公告)日：2012-02-14

    申请号：US13049464

    申请日：2011-03-16

    申请人： Akira Goda ,  Seiichi Aritome

    发明人： Akira Goda ,  Seiichi Aritome

    IPC分类号： G11C11/34

    CPC分类号： G11C16/3468

    摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for programming memory cells. One method includes determining a quantity of erase pulses used to place a group of memory cells of the array in an erased state, and adjusting at least one operating parameter associated with programming the group of memory cells at least partially based on the determined quantity of erase pulses.

    摘要翻译： 本公开的实施例提供用于编程存储器单元的方法，设备，模块和系统。 一种方法包括确定用于将阵列的一组存储器单元放置在擦除状态中的擦除脉冲的量，以及至少部分地基于确定的擦除量来调整与编程存储器单元组相关联的至少一个操作参数 脉冲。

    Memory Device Having Buried Boosting Plate and Methods of Operating the Same
    89.
    发明申请
    Memory Device Having Buried Boosting Plate and Methods of Operating the Same 有权
    具有埋入板的存储器件及其操作方法

    公开(公告)号：US20100232235A1

    公开(公告)日：2010-09-16

    申请号：US12402300

    申请日：2009-03-11

    申请人： Akira Goda

    发明人： Akira Goda

    IPC分类号： G11C16/06 ,  H01L29/788

    CPC分类号： G11C16/10 ,  H01L21/84 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/1203

    摘要： Memory devices are disclosed, such as those that include a semiconductor-on-insulator (SOI) NAND memory array having a boosting plate. The boosting plate may be disposed in an insulator layer of the SOI substrate such that the boosting plate exerts a capacitive coupling effect on a p-well of the memory array. Such a boosting plate may be used to boost the p-well during program and erase operations of the memory array. During a read operation, the boosting plate may be grounded to minimize interaction with p-well. Systems including the memory array and methods of operating the memory array are also disclosed.

    摘要翻译： 公开了存储器件，例如包括具有升压板的绝缘体上半导体（SOI）NAND存储器阵列的存储器件。 升压板可以设置在SOI衬底的绝缘体层中，使得升压板对存储器阵列的p阱施加电容耦合效应。 这种升压板可用于在存储器阵列的编程和擦除操作期间升压p阱。 在读取操作期间，升压板可以接地以最小化与p阱的相互作用。 还公开了包括存储器阵列的系统和操作存储器阵列的方法。

    Multilevel memory cell operation
    90.
    发明授权
    Multilevel memory cell operation 有权
    多层存储单元操作

    公开(公告)号：US07675772B2

    公开(公告)日：2010-03-09

    申请号：US11924793

    申请日：2007-10-26

    申请人： Akira Goda ,  Seiichi Aritome

    发明人： Akira Goda ,  Seiichi Aritome

    IPC分类号： G11C11/34

    CPC分类号： G11C16/349 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C2211/5634

    摘要： One or more embodiments of the present disclosure provide methods, devices, and systems for operating non-volatile multilevel memory cells. One method embodiment includes programming a memory cell to one of a number of different threshold voltage (Vt) levels, each level corresponding to a program state. The method includes programming a reference cell to a Vt level at least as great as an uppermost Vt level of the number of different Vt levels, performing a read operation on the reference cell, and determining a number of read reference voltages used to determine a particular program state of the memory cell based on the read operation performed on the reference cell.

    摘要翻译： 本公开的一个或多个实施例提供了用于操作非易失性多电平存储器单元的方法，装置和系统。 一个方法实施例包括将存储器单元编程为多个不同阈值电压（Vt）电平之一，每个电平对应于编程状态。 该方法包括将参考单元编程至至少与不同Vt电平数量的最高Vt电平一样大的Vt电平，对参考单元执行读取操作，以及确定用于确定特定值的读取参考电压的数量 基于对参考单元执行的读取操作，存储器单元的编程状态。